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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE4; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefix=AVX5; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX6; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512dq,+avx512bw | FileCheck %s --check-prefix=AVX7 8define <4 x i32> @add_op1_constant(ptr %p) nounwind {9; SSE-LABEL: add_op1_constant:10; SSE: # %bb.0:11; SSE-NEXT: movl (%rdi), %eax12; SSE-NEXT: addl $42, %eax13; SSE-NEXT: movd %eax, %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: add_op1_constant:17; AVX: # %bb.0:18; AVX-NEXT: movl (%rdi), %eax19; AVX-NEXT: addl $42, %eax20; AVX-NEXT: vmovd %eax, %xmm021; AVX-NEXT: retq22 %x = load i32, ptr %p23 %b = add i32 %x, 4224 %r = insertelement <4 x i32> undef, i32 %b, i32 025 ret <4 x i32> %r26}27 28; Code and data size may increase by using more vector ops, so the transform is disabled here.29 30define <4 x i32> @add_op1_constant_optsize(ptr %p) nounwind optsize {31; SSE-LABEL: add_op1_constant_optsize:32; SSE: # %bb.0:33; SSE-NEXT: movl (%rdi), %eax34; SSE-NEXT: addl $42, %eax35; SSE-NEXT: movd %eax, %xmm036; SSE-NEXT: retq37;38; AVX-LABEL: add_op1_constant_optsize:39; AVX: # %bb.0:40; AVX-NEXT: movl (%rdi), %eax41; AVX-NEXT: addl $42, %eax42; AVX-NEXT: vmovd %eax, %xmm043; AVX-NEXT: retq44 %x = load i32, ptr %p45 %b = add i32 %x, 4246 %r = insertelement <4 x i32> undef, i32 %b, i32 047 ret <4 x i32> %r48}49 50define <8 x i16> @add_op0_constant(ptr %p) nounwind {51; SSE-LABEL: add_op0_constant:52; SSE: # %bb.0:53; SSE-NEXT: movzwl (%rdi), %eax54; SSE-NEXT: addl $42, %eax55; SSE-NEXT: movd %eax, %xmm056; SSE-NEXT: retq57;58; AVX-LABEL: add_op0_constant:59; AVX: # %bb.0:60; AVX-NEXT: movzwl (%rdi), %eax61; AVX-NEXT: addl $42, %eax62; AVX-NEXT: vmovd %eax, %xmm063; AVX-NEXT: retq64 %x = load i16, ptr %p65 %b = add i16 42, %x66 %r = insertelement <8 x i16> undef, i16 %b, i32 067 ret <8 x i16> %r68}69 70define <2 x i64> @sub_op0_constant(ptr %p) nounwind {71; SSE-LABEL: sub_op0_constant:72; SSE: # %bb.0:73; SSE-NEXT: movl $42, %eax74; SSE-NEXT: subq (%rdi), %rax75; SSE-NEXT: movq %rax, %xmm076; SSE-NEXT: retq77;78; AVX-LABEL: sub_op0_constant:79; AVX: # %bb.0:80; AVX-NEXT: movl $42, %eax81; AVX-NEXT: subq (%rdi), %rax82; AVX-NEXT: vmovq %rax, %xmm083; AVX-NEXT: retq84 %x = load i64, ptr %p85 %b = sub i64 42, %x86 %r = insertelement <2 x i64> undef, i64 %b, i32 087 ret <2 x i64> %r88}89 90define <16 x i8> @sub_op1_constant(ptr %p) nounwind {91; SSE-LABEL: sub_op1_constant:92; SSE: # %bb.0:93; SSE-NEXT: movzbl (%rdi), %eax94; SSE-NEXT: addb $-42, %al95; SSE-NEXT: movzbl %al, %eax96; SSE-NEXT: movd %eax, %xmm097; SSE-NEXT: retq98;99; AVX-LABEL: sub_op1_constant:100; AVX: # %bb.0:101; AVX-NEXT: movzbl (%rdi), %eax102; AVX-NEXT: addb $-42, %al103; AVX-NEXT: vmovd %eax, %xmm0104; AVX-NEXT: retq105 %x = load i8, ptr %p106 %b = sub i8 %x, 42107 %r = insertelement <16 x i8> undef, i8 %b, i32 0108 ret <16 x i8> %r109}110 111define <4 x i32> @mul_op1_constant(ptr %p) nounwind {112; SSE-LABEL: mul_op1_constant:113; SSE: # %bb.0:114; SSE-NEXT: imull $42, (%rdi), %eax115; SSE-NEXT: movd %eax, %xmm0116; SSE-NEXT: retq117;118; AVX-LABEL: mul_op1_constant:119; AVX: # %bb.0:120; AVX-NEXT: imull $42, (%rdi), %eax121; AVX-NEXT: vmovd %eax, %xmm0122; AVX-NEXT: retq123 %x = load i32, ptr %p124 %b = mul i32 %x, 42125 %r = insertelement <4 x i32> undef, i32 %b, i32 0126 ret <4 x i32> %r127}128 129define <8 x i16> @mul_op0_constant(ptr %p) nounwind {130; SSE-LABEL: mul_op0_constant:131; SSE: # %bb.0:132; SSE-NEXT: movzwl (%rdi), %eax133; SSE-NEXT: imull $42, %eax, %eax134; SSE-NEXT: movd %eax, %xmm0135; SSE-NEXT: retq136;137; AVX-LABEL: mul_op0_constant:138; AVX: # %bb.0:139; AVX-NEXT: movzwl (%rdi), %eax140; AVX-NEXT: imull $42, %eax, %eax141; AVX-NEXT: vmovd %eax, %xmm0142; AVX-NEXT: retq143 %x = load i16, ptr %p144 %b = mul i16 42, %x145 %r = insertelement <8 x i16> undef, i16 %b, i32 0146 ret <8 x i16> %r147}148 149define <4 x i32> @and_op1_constant(ptr %p) nounwind {150; SSE-LABEL: and_op1_constant:151; SSE: # %bb.0:152; SSE-NEXT: movl (%rdi), %eax153; SSE-NEXT: andl $42, %eax154; SSE-NEXT: movd %eax, %xmm0155; SSE-NEXT: retq156;157; AVX-LABEL: and_op1_constant:158; AVX: # %bb.0:159; AVX-NEXT: movl (%rdi), %eax160; AVX-NEXT: andl $42, %eax161; AVX-NEXT: vmovd %eax, %xmm0162; AVX-NEXT: retq163 %x = load i32, ptr %p164 %b = and i32 %x, 42165 %r = insertelement <4 x i32> undef, i32 %b, i32 0166 ret <4 x i32> %r167}168 169define <2 x i64> @or_op1_constant(ptr %p) nounwind {170; SSE-LABEL: or_op1_constant:171; SSE: # %bb.0:172; SSE-NEXT: movq (%rdi), %rax173; SSE-NEXT: orq $42, %rax174; SSE-NEXT: movq %rax, %xmm0175; SSE-NEXT: retq176;177; AVX-LABEL: or_op1_constant:178; AVX: # %bb.0:179; AVX-NEXT: movq (%rdi), %rax180; AVX-NEXT: orq $42, %rax181; AVX-NEXT: vmovq %rax, %xmm0182; AVX-NEXT: retq183 %x = load i64, ptr %p184 %b = or i64 %x, 42185 %r = insertelement <2 x i64> undef, i64 %b, i32 0186 ret <2 x i64> %r187}188 189define <8 x i16> @xor_op1_constant(ptr %p) nounwind {190; SSE-LABEL: xor_op1_constant:191; SSE: # %bb.0:192; SSE-NEXT: movzwl (%rdi), %eax193; SSE-NEXT: xorl $42, %eax194; SSE-NEXT: movd %eax, %xmm0195; SSE-NEXT: retq196;197; AVX-LABEL: xor_op1_constant:198; AVX: # %bb.0:199; AVX-NEXT: movzwl (%rdi), %eax200; AVX-NEXT: xorl $42, %eax201; AVX-NEXT: vmovd %eax, %xmm0202; AVX-NEXT: retq203 %x = load i16, ptr %p204 %b = xor i16 %x, 42205 %r = insertelement <8 x i16> undef, i16 %b, i32 0206 ret <8 x i16> %r207}208 209define <4 x i32> @shl_op0_constant(ptr %p) nounwind {210; SSE-LABEL: shl_op0_constant:211; SSE: # %bb.0:212; SSE-NEXT: movzbl (%rdi), %ecx213; SSE-NEXT: movl $42, %eax214; SSE-NEXT: shll %cl, %eax215; SSE-NEXT: movd %eax, %xmm0216; SSE-NEXT: retq217;218; AVX-LABEL: shl_op0_constant:219; AVX: # %bb.0:220; AVX-NEXT: movzbl (%rdi), %ecx221; AVX-NEXT: movl $42, %eax222; AVX-NEXT: shll %cl, %eax223; AVX-NEXT: vmovd %eax, %xmm0224; AVX-NEXT: retq225 %x = load i32, ptr %p226 %b = shl i32 42, %x227 %r = insertelement <4 x i32> undef, i32 %b, i32 0228 ret <4 x i32> %r229}230 231define <16 x i8> @shl_op1_constant(ptr %p) nounwind {232; SSE-LABEL: shl_op1_constant:233; SSE: # %bb.0:234; SSE-NEXT: movzbl (%rdi), %eax235; SSE-NEXT: shlb $5, %al236; SSE-NEXT: movzbl %al, %eax237; SSE-NEXT: movd %eax, %xmm0238; SSE-NEXT: retq239;240; AVX-LABEL: shl_op1_constant:241; AVX: # %bb.0:242; AVX-NEXT: movzbl (%rdi), %eax243; AVX-NEXT: shlb $5, %al244; AVX-NEXT: vmovd %eax, %xmm0245; AVX-NEXT: retq246 %x = load i8, ptr %p247 %b = shl i8 %x, 5248 %r = insertelement <16 x i8> undef, i8 %b, i32 0249 ret <16 x i8> %r250}251 252define <2 x i64> @lshr_op0_constant(ptr %p) nounwind {253; SSE-LABEL: lshr_op0_constant:254; SSE: # %bb.0:255; SSE-NEXT: movzbl (%rdi), %ecx256; SSE-NEXT: movl $42, %eax257; SSE-NEXT: shrq %cl, %rax258; SSE-NEXT: movd %eax, %xmm0259; SSE-NEXT: retq260;261; AVX-LABEL: lshr_op0_constant:262; AVX: # %bb.0:263; AVX-NEXT: movzbl (%rdi), %ecx264; AVX-NEXT: movl $42, %eax265; AVX-NEXT: shrq %cl, %rax266; AVX-NEXT: vmovd %eax, %xmm0267; AVX-NEXT: retq268 %x = load i64, ptr %p269 %b = lshr i64 42, %x270 %r = insertelement <2 x i64> undef, i64 %b, i32 0271 ret <2 x i64> %r272}273 274define <4 x i32> @lshr_op1_constant(ptr %p) nounwind {275; SSE-LABEL: lshr_op1_constant:276; SSE: # %bb.0:277; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero278; SSE-NEXT: psrld $17, %xmm0279; SSE-NEXT: retq280;281; AVX-LABEL: lshr_op1_constant:282; AVX: # %bb.0:283; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero284; AVX-NEXT: vpsrld $17, %xmm0, %xmm0285; AVX-NEXT: retq286 %x = load i32, ptr %p287 %b = lshr i32 %x, 17288 %r = insertelement <4 x i32> undef, i32 %b, i32 0289 ret <4 x i32> %r290}291 292define <8 x i16> @ashr_op0_constant(ptr %p) nounwind {293; SSE-LABEL: ashr_op0_constant:294; SSE: # %bb.0:295; SSE-NEXT: movzbl (%rdi), %ecx296; SSE-NEXT: movl $-42, %eax297; SSE-NEXT: sarl %cl, %eax298; SSE-NEXT: movd %eax, %xmm0299; SSE-NEXT: retq300;301; AVX-LABEL: ashr_op0_constant:302; AVX: # %bb.0:303; AVX-NEXT: movzbl (%rdi), %ecx304; AVX-NEXT: movl $-42, %eax305; AVX-NEXT: sarl %cl, %eax306; AVX-NEXT: vmovd %eax, %xmm0307; AVX-NEXT: retq308 %x = load i16, ptr %p309 %b = ashr i16 -42, %x310 %r = insertelement <8 x i16> undef, i16 %b, i32 0311 ret <8 x i16> %r312}313 314define <8 x i16> @ashr_op1_constant(ptr %p) nounwind {315; SSE-LABEL: ashr_op1_constant:316; SSE: # %bb.0:317; SSE-NEXT: movswl (%rdi), %eax318; SSE-NEXT: movd %eax, %xmm0319; SSE-NEXT: psrad $7, %xmm0320; SSE-NEXT: retq321;322; AVX-LABEL: ashr_op1_constant:323; AVX: # %bb.0:324; AVX-NEXT: movswl (%rdi), %eax325; AVX-NEXT: vmovd %eax, %xmm0326; AVX-NEXT: vpsrad $7, %xmm0, %xmm0327; AVX-NEXT: retq328 %x = load i16, ptr %p329 %b = ashr i16 %x, 7330 %r = insertelement <8 x i16> undef, i16 %b, i32 0331 ret <8 x i16> %r332}333 334define <4 x i32> @sdiv_op0_constant(ptr %p) nounwind {335; SSE-LABEL: sdiv_op0_constant:336; SSE: # %bb.0:337; SSE-NEXT: movl $42, %eax338; SSE-NEXT: xorl %edx, %edx339; SSE-NEXT: idivl (%rdi)340; SSE-NEXT: movd %eax, %xmm0341; SSE-NEXT: retq342;343; AVX-LABEL: sdiv_op0_constant:344; AVX: # %bb.0:345; AVX-NEXT: movl $42, %eax346; AVX-NEXT: xorl %edx, %edx347; AVX-NEXT: idivl (%rdi)348; AVX-NEXT: vmovd %eax, %xmm0349; AVX-NEXT: retq350 %x = load i32, ptr %p351 %b = sdiv i32 42, %x352 %r = insertelement <4 x i32> undef, i32 %b, i32 0353 ret <4 x i32> %r354}355 356define <8 x i16> @sdiv_op1_constant(ptr %p) nounwind {357; SSE-LABEL: sdiv_op1_constant:358; SSE: # %bb.0:359; SSE-NEXT: movswl (%rdi), %eax360; SSE-NEXT: imull $-15603, %eax, %ecx # imm = 0xC30D361; SSE-NEXT: shrl $16, %ecx362; SSE-NEXT: addl %eax, %ecx363; SSE-NEXT: movzwl %cx, %eax364; SSE-NEXT: movswl %ax, %ecx365; SSE-NEXT: shrl $15, %eax366; SSE-NEXT: sarl $5, %ecx367; SSE-NEXT: addl %eax, %ecx368; SSE-NEXT: movd %ecx, %xmm0369; SSE-NEXT: retq370;371; AVX-LABEL: sdiv_op1_constant:372; AVX: # %bb.0:373; AVX-NEXT: movswl (%rdi), %eax374; AVX-NEXT: imull $-15603, %eax, %ecx # imm = 0xC30D375; AVX-NEXT: shrl $16, %ecx376; AVX-NEXT: addl %eax, %ecx377; AVX-NEXT: movzwl %cx, %eax378; AVX-NEXT: movswl %ax, %ecx379; AVX-NEXT: shrl $15, %eax380; AVX-NEXT: sarl $5, %ecx381; AVX-NEXT: addl %eax, %ecx382; AVX-NEXT: vmovd %ecx, %xmm0383; AVX-NEXT: retq384 %x = load i16, ptr %p385 %b = sdiv i16 %x, 42386 %r = insertelement <8 x i16> undef, i16 %b, i32 0387 ret <8 x i16> %r388}389 390define <8 x i16> @srem_op0_constant(ptr %p) nounwind {391; SSE-LABEL: srem_op0_constant:392; SSE: # %bb.0:393; SSE-NEXT: movw $42, %ax394; SSE-NEXT: xorl %edx, %edx395; SSE-NEXT: idivw (%rdi)396; SSE-NEXT: # kill: def $dx killed $dx def $edx397; SSE-NEXT: movd %edx, %xmm0398; SSE-NEXT: retq399;400; AVX-LABEL: srem_op0_constant:401; AVX: # %bb.0:402; AVX-NEXT: movw $42, %ax403; AVX-NEXT: xorl %edx, %edx404; AVX-NEXT: idivw (%rdi)405; AVX-NEXT: # kill: def $dx killed $dx def $edx406; AVX-NEXT: vmovd %edx, %xmm0407; AVX-NEXT: retq408 %x = load i16, ptr %p409 %b = srem i16 42, %x410 %r = insertelement <8 x i16> undef, i16 %b, i32 0411 ret <8 x i16> %r412}413 414define <4 x i32> @srem_op1_constant(ptr %p) nounwind {415; SSE-LABEL: srem_op1_constant:416; SSE: # %bb.0:417; SSE-NEXT: movslq (%rdi), %rax418; SSE-NEXT: imulq $818089009, %rax, %rcx # imm = 0x30C30C31419; SSE-NEXT: movq %rcx, %rdx420; SSE-NEXT: shrq $63, %rdx421; SSE-NEXT: sarq $35, %rcx422; SSE-NEXT: addl %edx, %ecx423; SSE-NEXT: imull $42, %ecx, %ecx424; SSE-NEXT: subl %ecx, %eax425; SSE-NEXT: movd %eax, %xmm0426; SSE-NEXT: retq427;428; AVX-LABEL: srem_op1_constant:429; AVX: # %bb.0:430; AVX-NEXT: movslq (%rdi), %rax431; AVX-NEXT: imulq $818089009, %rax, %rcx # imm = 0x30C30C31432; AVX-NEXT: movq %rcx, %rdx433; AVX-NEXT: shrq $63, %rdx434; AVX-NEXT: sarq $35, %rcx435; AVX-NEXT: addl %edx, %ecx436; AVX-NEXT: imull $42, %ecx, %ecx437; AVX-NEXT: subl %ecx, %eax438; AVX-NEXT: vmovd %eax, %xmm0439; AVX-NEXT: retq440 %x = load i32, ptr %p441 %b = srem i32 %x, 42442 %r = insertelement <4 x i32> undef, i32 %b, i32 0443 ret <4 x i32> %r444}445 446define <4 x i32> @udiv_op0_constant(ptr %p) nounwind {447; SSE-LABEL: udiv_op0_constant:448; SSE: # %bb.0:449; SSE-NEXT: movl $42, %eax450; SSE-NEXT: xorl %edx, %edx451; SSE-NEXT: divl (%rdi)452; SSE-NEXT: movd %eax, %xmm0453; SSE-NEXT: retq454;455; AVX-LABEL: udiv_op0_constant:456; AVX: # %bb.0:457; AVX-NEXT: movl $42, %eax458; AVX-NEXT: xorl %edx, %edx459; AVX-NEXT: divl (%rdi)460; AVX-NEXT: vmovd %eax, %xmm0461; AVX-NEXT: retq462 %x = load i32, ptr %p463 %b = udiv i32 42, %x464 %r = insertelement <4 x i32> undef, i32 %b, i32 0465 ret <4 x i32> %r466}467 468define <2 x i64> @udiv_op1_constant(ptr %p) nounwind {469; SSE-LABEL: udiv_op1_constant:470; SSE: # %bb.0:471; SSE-NEXT: movq (%rdi), %rax472; SSE-NEXT: shrq %rax473; SSE-NEXT: movabsq $-4392081922311798003, %rcx # imm = 0xC30C30C30C30C30D474; SSE-NEXT: mulq %rcx475; SSE-NEXT: movq %rdx, %xmm0476; SSE-NEXT: psrlq $4, %xmm0477; SSE-NEXT: retq478;479; AVX-LABEL: udiv_op1_constant:480; AVX: # %bb.0:481; AVX-NEXT: movq (%rdi), %rax482; AVX-NEXT: shrq %rax483; AVX-NEXT: movabsq $-4392081922311798003, %rcx # imm = 0xC30C30C30C30C30D484; AVX-NEXT: mulq %rcx485; AVX-NEXT: vmovq %rdx, %xmm0486; AVX-NEXT: vpsrlq $4, %xmm0, %xmm0487; AVX-NEXT: retq488 %x = load i64, ptr %p489 %b = udiv i64 %x, 42490 %r = insertelement <2 x i64> undef, i64 %b, i32 0491 ret <2 x i64> %r492}493 494define <2 x i64> @urem_op0_constant(ptr %p) nounwind {495; SSE-LABEL: urem_op0_constant:496; SSE: # %bb.0:497; SSE-NEXT: movl $42, %eax498; SSE-NEXT: xorl %edx, %edx499; SSE-NEXT: divq (%rdi)500; SSE-NEXT: movq %rdx, %xmm0501; SSE-NEXT: retq502;503; AVX-LABEL: urem_op0_constant:504; AVX: # %bb.0:505; AVX-NEXT: movl $42, %eax506; AVX-NEXT: xorl %edx, %edx507; AVX-NEXT: divq (%rdi)508; AVX-NEXT: vmovq %rdx, %xmm0509; AVX-NEXT: retq510 %x = load i64, ptr %p511 %b = urem i64 42, %x512 %r = insertelement <2 x i64> undef, i64 %b, i32 0513 ret <2 x i64> %r514}515 516define <16 x i8> @urem_op1_constant(ptr %p) nounwind {517; SSE-LABEL: urem_op1_constant:518; SSE: # %bb.0:519; SSE-NEXT: movzbl (%rdi), %eax520; SSE-NEXT: movl %eax, %ecx521; SSE-NEXT: shrb %cl522; SSE-NEXT: movzbl %cl, %ecx523; SSE-NEXT: imull $49, %ecx, %ecx524; SSE-NEXT: shrl $10, %ecx525; SSE-NEXT: imull $42, %ecx, %ecx526; SSE-NEXT: subb %cl, %al527; SSE-NEXT: movzbl %al, %eax528; SSE-NEXT: movd %eax, %xmm0529; SSE-NEXT: retq530;531; AVX-LABEL: urem_op1_constant:532; AVX: # %bb.0:533; AVX-NEXT: movzbl (%rdi), %eax534; AVX-NEXT: movl %eax, %ecx535; AVX-NEXT: shrb %cl536; AVX-NEXT: movzbl %cl, %ecx537; AVX-NEXT: imull $49, %ecx, %ecx538; AVX-NEXT: shrl $10, %ecx539; AVX-NEXT: imull $42, %ecx, %ecx540; AVX-NEXT: subb %cl, %al541; AVX-NEXT: vmovd %eax, %xmm0542; AVX-NEXT: retq543 %x = load i8, ptr %p544 %b = urem i8 %x, 42545 %r = insertelement <16 x i8> undef, i8 %b, i32 0546 ret <16 x i8> %r547}548 549define <4 x float> @fadd_op1_constant(ptr %p) nounwind {550; SSE-LABEL: fadd_op1_constant:551; SSE: # %bb.0:552; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero553; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0554; SSE-NEXT: retq555;556; AVX-LABEL: fadd_op1_constant:557; AVX: # %bb.0:558; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero559; AVX-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0560; AVX-NEXT: retq561 %x = load float, ptr %p562 %b = fadd float %x, 42.0563 %r = insertelement <4 x float> undef, float %b, i32 0564 ret <4 x float> %r565}566 567define <2 x double> @fsub_op1_constant(ptr %p) nounwind {568; SSE-LABEL: fsub_op1_constant:569; SSE: # %bb.0:570; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero571; SSE-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0572; SSE-NEXT: retq573;574; AVX-LABEL: fsub_op1_constant:575; AVX: # %bb.0:576; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero577; AVX-NEXT: vaddsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0578; AVX-NEXT: retq579 %x = load double, ptr %p580 %b = fsub double %x, 42.0581 %r = insertelement <2 x double> undef, double %b, i32 0582 ret <2 x double> %r583}584 585define <4 x float> @fsub_op0_constant(ptr %p) nounwind {586; SSE-LABEL: fsub_op0_constant:587; SSE: # %bb.0:588; SSE-NEXT: movss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]589; SSE-NEXT: subss (%rdi), %xmm0590; SSE-NEXT: retq591;592; AVX-LABEL: fsub_op0_constant:593; AVX: # %bb.0:594; AVX-NEXT: vmovss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]595; AVX-NEXT: vsubss (%rdi), %xmm0, %xmm0596; AVX-NEXT: retq597 %x = load float, ptr %p598 %b = fsub float 42.0, %x599 %r = insertelement <4 x float> undef, float %b, i32 0600 ret <4 x float> %r601}602 603define <4 x float> @fmul_op1_constant(ptr %p) nounwind {604; SSE-LABEL: fmul_op1_constant:605; SSE: # %bb.0:606; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero607; SSE-NEXT: mulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0608; SSE-NEXT: retq609;610; AVX-LABEL: fmul_op1_constant:611; AVX: # %bb.0:612; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero613; AVX-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0614; AVX-NEXT: retq615 %x = load float, ptr %p616 %b = fmul float %x, 42.0617 %r = insertelement <4 x float> undef, float %b, i32 0618 ret <4 x float> %r619}620 621define <2 x double> @fdiv_op1_constant(ptr %p) nounwind {622; SSE-LABEL: fdiv_op1_constant:623; SSE: # %bb.0:624; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero625; SSE-NEXT: divsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0626; SSE-NEXT: retq627;628; AVX-LABEL: fdiv_op1_constant:629; AVX: # %bb.0:630; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero631; AVX-NEXT: vdivsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0632; AVX-NEXT: retq633 %x = load double, ptr %p634 %b = fdiv double %x, 42.0635 %r = insertelement <2 x double> undef, double %b, i32 0636 ret <2 x double> %r637}638 639define <4 x float> @fdiv_op0_constant(ptr %p) nounwind {640; SSE-LABEL: fdiv_op0_constant:641; SSE: # %bb.0:642; SSE-NEXT: movss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]643; SSE-NEXT: divss (%rdi), %xmm0644; SSE-NEXT: retq645;646; AVX-LABEL: fdiv_op0_constant:647; AVX: # %bb.0:648; AVX-NEXT: vmovss {{.*#+}} xmm0 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]649; AVX-NEXT: vdivss (%rdi), %xmm0, %xmm0650; AVX-NEXT: retq651 %x = load float, ptr %p652 %b = fdiv float 42.0, %x653 %r = insertelement <4 x float> undef, float %b, i32 0654 ret <4 x float> %r655}656 657define <4 x float> @frem_op1_constant(ptr %p) nounwind {658; SSE-LABEL: frem_op1_constant:659; SSE: # %bb.0:660; SSE-NEXT: pushq %rax661; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero662; SSE-NEXT: movss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]663; SSE-NEXT: callq fmodf@PLT664; SSE-NEXT: popq %rax665; SSE-NEXT: retq666;667; AVX-LABEL: frem_op1_constant:668; AVX: # %bb.0:669; AVX-NEXT: pushq %rax670; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero671; AVX-NEXT: vmovss {{.*#+}} xmm1 = [4.2E+1,0.0E+0,0.0E+0,0.0E+0]672; AVX-NEXT: callq fmodf@PLT673; AVX-NEXT: popq %rax674; AVX-NEXT: retq675 %x = load float, ptr %p676 %b = frem float %x, 42.0677 %r = insertelement <4 x float> undef, float %b, i32 0678 ret <4 x float> %r679}680 681define <2 x double> @frem_op0_constant(ptr %p) nounwind {682; SSE-LABEL: frem_op0_constant:683; SSE: # %bb.0:684; SSE-NEXT: pushq %rax685; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero686; SSE-NEXT: movsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]687; SSE-NEXT: callq fmod@PLT688; SSE-NEXT: popq %rax689; SSE-NEXT: retq690;691; AVX-LABEL: frem_op0_constant:692; AVX: # %bb.0:693; AVX-NEXT: pushq %rax694; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero695; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]696; AVX-NEXT: callq fmod@PLT697; AVX-NEXT: popq %rax698; AVX-NEXT: retq699 %x = load double, ptr %p700 %b = frem double 42.0, %x701 %r = insertelement <2 x double> undef, double %b, i32 0702 ret <2 x double> %r703}704 705; Try again with 256-bit types.706 707define <8 x i32> @add_op1_constant_v8i32(ptr %p) nounwind {708; SSE-LABEL: add_op1_constant_v8i32:709; SSE: # %bb.0:710; SSE-NEXT: movl (%rdi), %eax711; SSE-NEXT: addl $42, %eax712; SSE-NEXT: movd %eax, %xmm0713; SSE-NEXT: retq714;715; AVX-LABEL: add_op1_constant_v8i32:716; AVX: # %bb.0:717; AVX-NEXT: movl (%rdi), %eax718; AVX-NEXT: addl $42, %eax719; AVX-NEXT: vmovd %eax, %xmm0720; AVX-NEXT: retq721 %x = load i32, ptr %p722 %b = add i32 %x, 42723 %r = insertelement <8 x i32> undef, i32 %b, i32 0724 ret <8 x i32> %r725}726 727define <4 x i64> @sub_op0_constant_v4i64(ptr %p) nounwind {728; SSE-LABEL: sub_op0_constant_v4i64:729; SSE: # %bb.0:730; SSE-NEXT: movl $42, %eax731; SSE-NEXT: subq (%rdi), %rax732; SSE-NEXT: movq %rax, %xmm0733; SSE-NEXT: retq734;735; AVX-LABEL: sub_op0_constant_v4i64:736; AVX: # %bb.0:737; AVX-NEXT: movl $42, %eax738; AVX-NEXT: subq (%rdi), %rax739; AVX-NEXT: vmovq %rax, %xmm0740; AVX-NEXT: retq741 %x = load i64, ptr %p742 %b = sub i64 42, %x743 %r = insertelement <4 x i64> undef, i64 %b, i32 0744 ret <4 x i64> %r745}746 747define <8 x i32> @mul_op1_constant_v8i32(ptr %p) nounwind {748; SSE-LABEL: mul_op1_constant_v8i32:749; SSE: # %bb.0:750; SSE-NEXT: imull $42, (%rdi), %eax751; SSE-NEXT: movd %eax, %xmm0752; SSE-NEXT: retq753;754; AVX-LABEL: mul_op1_constant_v8i32:755; AVX: # %bb.0:756; AVX-NEXT: imull $42, (%rdi), %eax757; AVX-NEXT: vmovd %eax, %xmm0758; AVX-NEXT: retq759 %x = load i32, ptr %p760 %b = mul i32 %x, 42761 %r = insertelement <8 x i32> undef, i32 %b, i32 0762 ret <8 x i32> %r763}764 765define <4 x i64> @or_op1_constant_v4i64(ptr %p) nounwind {766; SSE-LABEL: or_op1_constant_v4i64:767; SSE: # %bb.0:768; SSE-NEXT: movq (%rdi), %rax769; SSE-NEXT: orq $42, %rax770; SSE-NEXT: movq %rax, %xmm0771; SSE-NEXT: retq772;773; AVX-LABEL: or_op1_constant_v4i64:774; AVX: # %bb.0:775; AVX-NEXT: movq (%rdi), %rax776; AVX-NEXT: orq $42, %rax777; AVX-NEXT: vmovq %rax, %xmm0778; AVX-NEXT: retq779 %x = load i64, ptr %p780 %b = or i64 %x, 42781 %r = insertelement <4 x i64> undef, i64 %b, i32 0782 ret <4 x i64> %r783}784 785; Try again with 512-bit types.786 787define <16 x i32> @add_op1_constant_v16i32(ptr %p) nounwind {788; SSE-LABEL: add_op1_constant_v16i32:789; SSE: # %bb.0:790; SSE-NEXT: movl (%rdi), %eax791; SSE-NEXT: addl $42, %eax792; SSE-NEXT: movd %eax, %xmm0793; SSE-NEXT: retq794;795; AVX-LABEL: add_op1_constant_v16i32:796; AVX: # %bb.0:797; AVX-NEXT: movl (%rdi), %eax798; AVX-NEXT: addl $42, %eax799; AVX-NEXT: vmovd %eax, %xmm0800; AVX-NEXT: retq801 %x = load i32, ptr %p802 %b = add i32 %x, 42803 %r = insertelement <16 x i32> undef, i32 %b, i32 0804 ret <16 x i32> %r805}806 807define <8 x i64> @sub_op0_constant_v8i64(ptr %p) nounwind {808; SSE-LABEL: sub_op0_constant_v8i64:809; SSE: # %bb.0:810; SSE-NEXT: movl $42, %eax811; SSE-NEXT: subq (%rdi), %rax812; SSE-NEXT: movq %rax, %xmm0813; SSE-NEXT: retq814;815; AVX-LABEL: sub_op0_constant_v8i64:816; AVX: # %bb.0:817; AVX-NEXT: movl $42, %eax818; AVX-NEXT: subq (%rdi), %rax819; AVX-NEXT: vmovq %rax, %xmm0820; AVX-NEXT: retq821 %x = load i64, ptr %p822 %b = sub i64 42, %x823 %r = insertelement <8 x i64> undef, i64 %b, i32 0824 ret <8 x i64> %r825}826 827define <16 x i32> @mul_op1_constant_v16i32(ptr %p) nounwind {828; SSE-LABEL: mul_op1_constant_v16i32:829; SSE: # %bb.0:830; SSE-NEXT: imull $42, (%rdi), %eax831; SSE-NEXT: movd %eax, %xmm0832; SSE-NEXT: retq833;834; AVX-LABEL: mul_op1_constant_v16i32:835; AVX: # %bb.0:836; AVX-NEXT: imull $42, (%rdi), %eax837; AVX-NEXT: vmovd %eax, %xmm0838; AVX-NEXT: retq839 %x = load i32, ptr %p840 %b = mul i32 %x, 42841 %r = insertelement <16 x i32> undef, i32 %b, i32 0842 ret <16 x i32> %r843}844 845define <8 x i64> @or_op1_constant_v8i64(ptr %p) nounwind {846; SSE-LABEL: or_op1_constant_v8i64:847; SSE: # %bb.0:848; SSE-NEXT: movq (%rdi), %rax849; SSE-NEXT: orq $42, %rax850; SSE-NEXT: movq %rax, %xmm0851; SSE-NEXT: retq852;853; AVX-LABEL: or_op1_constant_v8i64:854; AVX: # %bb.0:855; AVX-NEXT: movq (%rdi), %rax856; AVX-NEXT: orq $42, %rax857; AVX-NEXT: vmovq %rax, %xmm0858; AVX-NEXT: retq859 %x = load i64, ptr %p860 %b = or i64 %x, 42861 %r = insertelement <8 x i64> undef, i64 %b, i32 0862 ret <8 x i64> %r863}864 865