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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2,sse-unaligned-mem | FileCheck %s --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX4 5; Although we have the ability to fold an unaligned load with AVX6; and under special conditions with some SSE implementations, we7; can not fold the load under any circumstances in these test8; cases because they are not 16-byte loads. The load must be9; executed as a scalar ('movs*') with a zero extension to10; 128-bits and then used in the packed logical ('andp*') op.11; PR22371 - http://llvm.org/bugs/show_bug.cgi?id=2237112 13define double @load_double_no_fold(double %x, double %y) {14; SSE2-LABEL: load_double_no_fold:15; SSE2: # %bb.0:16; SSE2-NEXT: cmplesd %xmm0, %xmm117; SSE2-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]18; SSE2-NEXT: andpd %xmm1, %xmm019; SSE2-NEXT: retq20;21; AVX-LABEL: load_double_no_fold:22; AVX: # %bb.0:23; AVX-NEXT: vcmplesd %xmm0, %xmm1, %xmm024; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+0,0.0E+0]25; AVX-NEXT: vandpd %xmm1, %xmm0, %xmm026; AVX-NEXT: retq27 28 %cmp = fcmp oge double %x, %y29 %zext = zext i1 %cmp to i3230 %conv = sitofp i32 %zext to double31 ret double %conv32}33 34define float @load_float_no_fold(float %x, float %y) {35; SSE2-LABEL: load_float_no_fold:36; SSE2: # %bb.0:37; SSE2-NEXT: cmpless %xmm0, %xmm138; SSE2-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]39; SSE2-NEXT: andps %xmm1, %xmm040; SSE2-NEXT: retq41;42; AVX-LABEL: load_float_no_fold:43; AVX: # %bb.0:44; AVX-NEXT: vcmpless %xmm0, %xmm1, %xmm045; AVX-NEXT: vmovss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]46; AVX-NEXT: vandps %xmm1, %xmm0, %xmm047; AVX-NEXT: retq48 49 %cmp = fcmp oge float %x, %y50 %zext = zext i1 %cmp to i3251 %conv = sitofp i32 %zext to float52 ret float %conv53}54 55