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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE23; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX4 5define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {6; SSE2-LABEL: test1:7; SSE2: # %bb.0: # %entry8; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]9; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero10; SSE2-NEXT: psllw %xmm1, %xmm011; SSE2-NEXT: retq12;13; AVX-LABEL: test1:14; AVX: # %bb.0: # %entry15; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero16; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm017; AVX-NEXT: retq18entry:19 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer20 %shl = shl <8 x i16> %A, %vecinit1421 ret <8 x i16> %shl22}23 24define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {25; SSE2-LABEL: test2:26; SSE2: # %bb.0: # %entry27; SSE2-NEXT: xorps %xmm2, %xmm228; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]29; SSE2-NEXT: pslld %xmm2, %xmm030; SSE2-NEXT: retq31;32; AVX-LABEL: test2:33; AVX: # %bb.0: # %entry34; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero35; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm036; AVX-NEXT: retq37entry:38 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer39 %shl = shl <4 x i32> %A, %vecinit640 ret <4 x i32> %shl41}42 43define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {44; SSE2-LABEL: test3:45; SSE2: # %bb.0: # %entry46; SSE2-NEXT: psllq %xmm1, %xmm047; SSE2-NEXT: retq48;49; AVX-LABEL: test3:50; AVX: # %bb.0: # %entry51; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm052; AVX-NEXT: retq53entry:54 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer55 %shl = shl <2 x i64> %A, %vecinit256 ret <2 x i64> %shl57}58 59define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {60; SSE2-LABEL: test4:61; SSE2: # %bb.0: # %entry62; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]63; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero64; SSE2-NEXT: psrlw %xmm1, %xmm065; SSE2-NEXT: retq66;67; AVX-LABEL: test4:68; AVX: # %bb.0: # %entry69; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero70; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm071; AVX-NEXT: retq72entry:73 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer74 %shr = lshr <8 x i16> %A, %vecinit1475 ret <8 x i16> %shr76}77 78define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {79; SSE2-LABEL: test5:80; SSE2: # %bb.0: # %entry81; SSE2-NEXT: xorps %xmm2, %xmm282; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]83; SSE2-NEXT: psrld %xmm2, %xmm084; SSE2-NEXT: retq85;86; AVX-LABEL: test5:87; AVX: # %bb.0: # %entry88; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero89; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm090; AVX-NEXT: retq91entry:92 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer93 %shr = lshr <4 x i32> %A, %vecinit694 ret <4 x i32> %shr95}96 97define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {98; SSE2-LABEL: test6:99; SSE2: # %bb.0: # %entry100; SSE2-NEXT: psrlq %xmm1, %xmm0101; SSE2-NEXT: retq102;103; AVX-LABEL: test6:104; AVX: # %bb.0: # %entry105; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0106; AVX-NEXT: retq107entry:108 %vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer109 %shr = lshr <2 x i64> %A, %vecinit2110 ret <2 x i64> %shr111}112 113define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {114; SSE2-LABEL: test7:115; SSE2: # %bb.0: # %entry116; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]117; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero118; SSE2-NEXT: psraw %xmm1, %xmm0119; SSE2-NEXT: retq120;121; AVX-LABEL: test7:122; AVX: # %bb.0: # %entry123; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero124; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0125; AVX-NEXT: retq126entry:127 %vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer128 %shr = ashr <8 x i16> %A, %vecinit14129 ret <8 x i16> %shr130}131 132define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {133; SSE2-LABEL: test8:134; SSE2: # %bb.0: # %entry135; SSE2-NEXT: xorps %xmm2, %xmm2136; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]137; SSE2-NEXT: psrad %xmm2, %xmm0138; SSE2-NEXT: retq139;140; AVX-LABEL: test8:141; AVX: # %bb.0: # %entry142; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero143; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0144; AVX-NEXT: retq145entry:146 %vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer147 %shr = ashr <4 x i32> %A, %vecinit6148 ret <4 x i32> %shr149}150