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1; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -mattr=+lvi-load-hardening -mattr=+lvi-cfi -x86-experimental-lvi-inline-asm-hardening < %s -o %t.out 2> %t.err2; RUN: FileCheck %s --check-prefix=X86 < %t.out3; RUN: FileCheck %s --check-prefix=WARN < %t.err4 5; Test module-level assembly6module asm "pop %rbx"7module asm "ret"8; X86: popq %rbx9; X86-NEXT: lfence10; X86-NEXT: shlq $0, (%rsp)11; X86-NEXT: lfence12; X86-NEXT: retq13 14; Function Attrs: noinline nounwind optnone uwtable15define dso_local void @test_inline_asm() {16entry:17; X86-LABEL: test_inline_asm:18 call void asm sideeffect "mov 0x3fed(%rip),%rax", "~{dirflag},~{fpsr},~{flags}"() #119; X86: movq 16365(%rip), %rax20; X86-NEXT: lfence21 call void asm sideeffect "movdqa 0x0(%rip),%xmm0", "~{dirflag},~{fpsr},~{flags}"() #122; X86: movdqa (%rip), %xmm023; X86-NEXT: lfence24 call void asm sideeffect "movslq 0x3e5d(%rip),%rbx", "~{dirflag},~{fpsr},~{flags}"() #125; X86: movslq 15965(%rip), %rbx26; X86-NEXT: lfence27 call void asm sideeffect "mov (%r12,%rax,8),%rax", "~{dirflag},~{fpsr},~{flags}"() #128; X86: movq (%r12,%rax,8), %rax29; X86-NEXT: lfence30 call void asm sideeffect "movq (24)(%rsi), %r11", "~{dirflag},~{fpsr},~{flags}"() #131; X86: movq 24(%rsi), %r1132; X86-NEXT: lfence33 call void asm sideeffect "cmove %r12,%rax", "~{dirflag},~{fpsr},~{flags}"() #134; X86: cmoveq %r12, %rax35; X86-NOT: lfence36 call void asm sideeffect "cmove (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #137; X86: cmoveq (%r12), %rax38; X86-NEXT: lfence39 call void asm sideeffect "pop %rbx", "~{dirflag},~{fpsr},~{flags}"() #140; X86: popq %rbx41; X86-NEXT: lfence42 call void asm sideeffect "popq %rbx", "~{dirflag},~{fpsr},~{flags}"() #143; X86: popq %rbx44; X86-NEXT: lfence45 call void asm sideeffect "xchg (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #146; X86: xchgq %rax, (%r12)47; X86-NEXT: lfence48 call void asm sideeffect "cmpxchg %r12,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #149; X86: cmpxchgq %r12, (%rax)50; X86-NEXT: lfence51 call void asm sideeffect "vpxor (%rcx,%rdx,1),%ymm1,%ymm0", "~{dirflag},~{fpsr},~{flags}"() #152; X86: vpxor (%rcx,%rdx), %ymm1, %ymm053; X86-NEXT: lfence54 call void asm sideeffect "vpmuludq 0x20(%rsi),%ymm0,%ymm12", "~{dirflag},~{fpsr},~{flags}"() #155; X86: vpmuludq 32(%rsi), %ymm0, %ymm1256; X86-NEXT: lfence57 call void asm sideeffect "vpexpandq 0x40(%rdi),%zmm8{%k2}{z}", "~{dirflag},~{fpsr},~{flags}"() #158; X86: vpexpandq 64(%rdi), %zmm8 {%k2} {z}59; X86-NEXT: lfence60 call void asm sideeffect "addq (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #161; X86: addq (%r12), %rax62; X86-NEXT: lfence63 call void asm sideeffect "subq Lpoly+0(%rip), %rax", "~{dirflag},~{fpsr},~{flags}"() #164; X86: subq Lpoly+0(%rip), %rax65; X86-NEXT: lfence66 call void asm sideeffect "adcq %r12,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #167; X86: adcq %r12, (%rax)68; X86-NEXT: lfence69 call void asm sideeffect "negq (%rax)", "~{dirflag},~{fpsr},~{flags}"() #170; X86: negq (%rax)71; X86-NEXT: lfence72 call void asm sideeffect "incq %rax", "~{dirflag},~{fpsr},~{flags}"() #173; X86: incq %rax74; X86-NOT: lfence75 call void asm sideeffect "mulq (%rax)", "~{dirflag},~{fpsr},~{flags}"() #176; X86: mulq (%rax)77; X86-NEXT: lfence78 call void asm sideeffect "imulq (%rax),%rdx", "~{dirflag},~{fpsr},~{flags}"() #179; X86: imulq (%rax), %rdx80; X86-NEXT: lfence81 call void asm sideeffect "shlq $$1,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #182; X86: shlq (%rax)83; X86-NEXT: lfence84 call void asm sideeffect "shrq $$1,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #185; X86: shrq (%rax)86; X86-NEXT: lfence87 call void asm sideeffect "repz cmpsb %es:(%rdi),%ds:(%rsi)", "~{dirflag},~{fpsr},~{flags}"() #188; WARN: warning: Instruction may be vulnerable to LVI89; WARN-NEXT: repz cmpsb %es:(%rdi),%ds:(%rsi)90; WARN-NEXT: ^91; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information92; X86: rep cmpsb %es:(%rdi), %ds:(%rsi)93; X86-NOT: lfence94 call void asm sideeffect "repnz scasb", "~{dirflag},~{fpsr},~{flags}"() #195; WARN: warning: Instruction may be vulnerable to LVI96; WARN-NEXT: repnz scasb97; WARN-NEXT: ^98; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information99; X86: repne scasb %es:(%rdi), %al100; X86-NOT: lfence101 call void asm sideeffect "repnz", ""() #1102; WARN: warning: Instruction may be vulnerable to LVI103; WARN-NEXT: repnz104; WARN-NEXT: ^105; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information106 call void asm sideeffect "pinsrw $$0x6,(%eax),%xmm0", "~{dirflag},~{fpsr},~{flags}"() #1107; X86: pinsrw $6, (%eax), %xmm0108; X86-NEXT: lfence109 call void asm sideeffect "ret", "~{dirflag},~{fpsr},~{flags}"() #1110; X86: shlq $0, (%rsp)111; X86-NEXT: lfence112; X86-NEXT: retq113; X86-NOT: lfence114 call void asm sideeffect "ret $$8", "~{dirflag},~{fpsr},~{flags}"() #1115; X86: shlq $0, (%rsp)116; X86-NEXT: lfence117; X86-NEXT: retq $8118; X86-NOT: lfence119 call void asm sideeffect "jmpq *(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1120; WARN: warning: Instruction may be vulnerable to LVI121; WARN-NEXT: jmpq *(%rdx)122; WARN-NEXT: ^123; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information124; X86: jmpq *(%rdx)125; X86-NOT: lfence126 call void asm sideeffect "jmpq *0x100(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1127; WARN: warning: Instruction may be vulnerable to LVI128; WARN-NEXT: jmpq *0x100(%rdx)129; WARN-NEXT: ^130; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information131; X86: jmpq *256(%rdx)132; X86-NOT: lfence133 call void asm sideeffect "callq *200(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1134; WARN: warning: Instruction may be vulnerable to LVI135; WARN-NEXT: callq *200(%rdx)136; WARN-NEXT: ^137; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information138; X86: callq *200(%rdx)139; X86-NOT: lfence140 call void asm sideeffect "fldt 0x8(%rbp)", "~{dirflag},~{fpsr},~{flags}"() #1141; X86: fldt 8(%rbp)142; X86-NEXT: lfence143 call void asm sideeffect "fld %st(0)", "~{dirflag},~{fpsr},~{flags}"() #1144; X86: fld %st(0)145; X86-NOT: lfence146; Test assembler macros147 call void asm sideeffect ".macro mplus1 x\0Aincq (\5Cx)\0A.endm\0Amplus1 %rcx", "~{dirflag},~{fpsr},~{flags}"() #1148; X86: incq (%rcx)149; X86-NEXT: lfence150 ret void151}152 153attributes #1 = { nounwind }154