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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefix=SSE3; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefixes=AVX,AVX14; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx512vl -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -machine-combiner-verify-pattern-order=true < %s | FileCheck %s --check-prefixes=AVX,AVX5125 6; Incremental updates of the instruction depths should be enough for this test7; case.8; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mattr=sse -machine-combiner-inc-threshold=0 < %s | FileCheck %s --check-prefix=SSE9; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mattr=avx -machine-combiner-inc-threshold=0 < %s | FileCheck %s --check-prefixes=AVX,AVX110; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -mattr=avx512vl -machine-combiner-inc-threshold=0 < %s | FileCheck %s --check-prefixes=AVX,AVX51211 12; Verify that the first two adds are independent regardless of how the inputs are13; commuted. The destination registers are used as source registers for the third add.14 15define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {16; SSE-LABEL: reassociate_adds1:17; SSE: # %bb.0:18; SSE-NEXT: addss %xmm1, %xmm019; SSE-NEXT: addss %xmm3, %xmm220; SSE-NEXT: addss %xmm2, %xmm021; SSE-NEXT: retq22;23; AVX-LABEL: reassociate_adds1:24; AVX: # %bb.0:25; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm026; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm127; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm028; AVX-NEXT: retq29 %t0 = fadd reassoc nsz float %x0, %x130 %t1 = fadd reassoc nsz float %t0, %x231 %t2 = fadd reassoc nsz float %t1, %x332 ret float %t233}34 35define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {36; SSE-LABEL: reassociate_adds2:37; SSE: # %bb.0:38; SSE-NEXT: addss %xmm1, %xmm039; SSE-NEXT: addss %xmm3, %xmm240; SSE-NEXT: addss %xmm2, %xmm041; SSE-NEXT: retq42;43; AVX-LABEL: reassociate_adds2:44; AVX: # %bb.0:45; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm046; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm147; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm048; AVX-NEXT: retq49 %t0 = fadd reassoc nsz float %x0, %x150 %t1 = fadd reassoc nsz float %x2, %t051 %t2 = fadd reassoc nsz float %t1, %x352 ret float %t253}54 55define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {56; SSE-LABEL: reassociate_adds3:57; SSE: # %bb.0:58; SSE-NEXT: addss %xmm1, %xmm059; SSE-NEXT: addss %xmm3, %xmm260; SSE-NEXT: addss %xmm2, %xmm061; SSE-NEXT: retq62;63; AVX-LABEL: reassociate_adds3:64; AVX: # %bb.0:65; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm066; AVX-NEXT: vaddss %xmm2, %xmm3, %xmm167; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm068; AVX-NEXT: retq69 %t0 = fadd reassoc nsz float %x0, %x170 %t1 = fadd reassoc nsz float %t0, %x271 %t2 = fadd reassoc nsz float %x3, %t172 ret float %t273}74 75define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {76; SSE-LABEL: reassociate_adds4:77; SSE: # %bb.0:78; SSE-NEXT: addss %xmm1, %xmm079; SSE-NEXT: addss %xmm3, %xmm280; SSE-NEXT: addss %xmm2, %xmm081; SSE-NEXT: retq82;83; AVX-LABEL: reassociate_adds4:84; AVX: # %bb.0:85; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm086; AVX-NEXT: vaddss %xmm2, %xmm3, %xmm187; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm088; AVX-NEXT: retq89 %t0 = fadd reassoc nsz float %x0, %x190 %t1 = fadd reassoc nsz float %x2, %t091 %t2 = fadd reassoc nsz float %x3, %t192 ret float %t293}94 95; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not96; produced because that would cost more compile time.97 98define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {99; SSE-LABEL: reassociate_adds5:100; SSE: # %bb.0:101; SSE-NEXT: addss %xmm1, %xmm0102; SSE-NEXT: addss %xmm3, %xmm2103; SSE-NEXT: addss %xmm2, %xmm0104; SSE-NEXT: addss %xmm5, %xmm4105; SSE-NEXT: addss %xmm6, %xmm4106; SSE-NEXT: addss %xmm4, %xmm0107; SSE-NEXT: addss %xmm7, %xmm0108; SSE-NEXT: retq109;110; AVX-LABEL: reassociate_adds5:111; AVX: # %bb.0:112; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0113; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm1114; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0115; AVX-NEXT: vaddss %xmm5, %xmm4, %xmm1116; AVX-NEXT: vaddss %xmm6, %xmm1, %xmm1117; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0118; AVX-NEXT: vaddss %xmm7, %xmm0, %xmm0119; AVX-NEXT: retq120 %t0 = fadd reassoc nsz float %x0, %x1121 %t1 = fadd reassoc nsz float %t0, %x2122 %t2 = fadd reassoc nsz float %t1, %x3123 %t3 = fadd reassoc nsz float %t2, %x4124 %t4 = fadd reassoc nsz float %t3, %x5125 %t5 = fadd reassoc nsz float %t4, %x6126 %t6 = fadd reassoc nsz float %t5, %x7127 ret float %t6128}129 130; Verify that we only need two associative operations to reassociate the operands.131; Also, we should reassociate such that the result of the high latency division132; is used by the final 'add' rather than reassociating the %x3 operand with the133; division. The latter reassociation would not improve anything.134 135define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {136; SSE-LABEL: reassociate_adds6:137; SSE: # %bb.0:138; SSE-NEXT: divss %xmm1, %xmm0139; SSE-NEXT: addss %xmm3, %xmm2140; SSE-NEXT: addss %xmm2, %xmm0141; SSE-NEXT: retq142;143; AVX-LABEL: reassociate_adds6:144; AVX: # %bb.0:145; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0146; AVX-NEXT: vaddss %xmm2, %xmm3, %xmm1147; AVX-NEXT: vaddss %xmm0, %xmm1, %xmm0148; AVX-NEXT: retq149 %t0 = fdiv reassoc nsz float %x0, %x1150 %t1 = fadd reassoc nsz float %x2, %t0151 %t2 = fadd reassoc nsz float %x3, %t1152 ret float %t2153}154 155; Verify that SSE and AVX scalar single-precision multiplies are reassociated.156 157define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {158; SSE-LABEL: reassociate_muls1:159; SSE: # %bb.0:160; SSE-NEXT: divss %xmm1, %xmm0161; SSE-NEXT: mulss %xmm3, %xmm2162; SSE-NEXT: mulss %xmm2, %xmm0163; SSE-NEXT: retq164;165; AVX-LABEL: reassociate_muls1:166; AVX: # %bb.0:167; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0168; AVX-NEXT: vmulss %xmm2, %xmm3, %xmm1169; AVX-NEXT: vmulss %xmm0, %xmm1, %xmm0170; AVX-NEXT: retq171 %t0 = fdiv reassoc nsz float %x0, %x1172 %t1 = fmul reassoc nsz float %x2, %t0173 %t2 = fmul reassoc nsz float %x3, %t1174 ret float %t2175}176 177; Verify that SSE and AVX scalar double-precision adds are reassociated.178 179define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {180; SSE-LABEL: reassociate_adds_double:181; SSE: # %bb.0:182; SSE-NEXT: divsd %xmm1, %xmm0183; SSE-NEXT: addsd %xmm3, %xmm2184; SSE-NEXT: addsd %xmm2, %xmm0185; SSE-NEXT: retq186;187; AVX-LABEL: reassociate_adds_double:188; AVX: # %bb.0:189; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0190; AVX-NEXT: vaddsd %xmm2, %xmm3, %xmm1191; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm0192; AVX-NEXT: retq193 %t0 = fdiv reassoc nsz double %x0, %x1194 %t1 = fadd reassoc nsz double %x2, %t0195 %t2 = fadd reassoc nsz double %x3, %t1196 ret double %t2197}198 199; Verify that SSE and AVX scalar double-precision multiplies are reassociated.200 201define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {202; SSE-LABEL: reassociate_muls_double:203; SSE: # %bb.0:204; SSE-NEXT: divsd %xmm1, %xmm0205; SSE-NEXT: mulsd %xmm3, %xmm2206; SSE-NEXT: mulsd %xmm2, %xmm0207; SSE-NEXT: retq208;209; AVX-LABEL: reassociate_muls_double:210; AVX: # %bb.0:211; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0212; AVX-NEXT: vmulsd %xmm2, %xmm3, %xmm1213; AVX-NEXT: vmulsd %xmm0, %xmm1, %xmm0214; AVX-NEXT: retq215 %t0 = fdiv reassoc nsz double %x0, %x1216 %t1 = fmul reassoc nsz double %x2, %t0217 %t2 = fmul reassoc nsz double %x3, %t1218 ret double %t2219}220 221; Verify that SSE and AVX 128-bit vector single-precision adds are reassociated.222 223define <4 x float> @reassociate_adds_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {224; SSE-LABEL: reassociate_adds_v4f32:225; SSE: # %bb.0:226; SSE-NEXT: mulps %xmm1, %xmm0227; SSE-NEXT: addps %xmm3, %xmm2228; SSE-NEXT: addps %xmm2, %xmm0229; SSE-NEXT: retq230;231; AVX1-LABEL: reassociate_adds_v4f32:232; AVX1: # %bb.0:233; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0234; AVX1-NEXT: vaddps %xmm2, %xmm3, %xmm1235; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0236; AVX1-NEXT: retq237;238; AVX512-LABEL: reassociate_adds_v4f32:239; AVX512: # %bb.0:240; AVX512-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2241; AVX512-NEXT: vaddps %xmm0, %xmm3, %xmm0242; AVX512-NEXT: retq243 %t0 = fmul contract reassoc nsz <4 x float> %x0, %x1244 %t1 = fadd contract reassoc nsz <4 x float> %x2, %t0245 %t2 = fadd reassoc nsz <4 x float> %x3, %t1246 ret <4 x float> %t2247}248 249; Verify that SSE and AVX 128-bit vector double-precision adds are reassociated.250 251define <2 x double> @reassociate_adds_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {252; SSE-LABEL: reassociate_adds_v2f64:253; SSE: # %bb.0:254; SSE-NEXT: mulpd %xmm1, %xmm0255; SSE-NEXT: addpd %xmm3, %xmm2256; SSE-NEXT: addpd %xmm2, %xmm0257; SSE-NEXT: retq258;259; AVX1-LABEL: reassociate_adds_v2f64:260; AVX1: # %bb.0:261; AVX1-NEXT: vmulpd %xmm1, %xmm0, %xmm0262; AVX1-NEXT: vaddpd %xmm2, %xmm3, %xmm1263; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0264; AVX1-NEXT: retq265;266; AVX512-LABEL: reassociate_adds_v2f64:267; AVX512: # %bb.0:268; AVX512-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2269; AVX512-NEXT: vaddpd %xmm0, %xmm3, %xmm0270; AVX512-NEXT: retq271 %t0 = fmul contract reassoc nsz <2 x double> %x0, %x1272 %t1 = fadd contract reassoc nsz <2 x double> %x2, %t0273 %t2 = fadd reassoc nsz <2 x double> %x3, %t1274 ret <2 x double> %t2275}276 277; Verify that SSE and AVX 128-bit vector single-precision multiplies are reassociated.278 279define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {280; SSE-LABEL: reassociate_muls_v4f32:281; SSE: # %bb.0:282; SSE-NEXT: addps %xmm1, %xmm0283; SSE-NEXT: mulps %xmm3, %xmm2284; SSE-NEXT: mulps %xmm2, %xmm0285; SSE-NEXT: retq286;287; AVX-LABEL: reassociate_muls_v4f32:288; AVX: # %bb.0:289; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0290; AVX-NEXT: vmulps %xmm2, %xmm3, %xmm1291; AVX-NEXT: vmulps %xmm0, %xmm1, %xmm0292; AVX-NEXT: retq293 %t0 = fadd reassoc nsz <4 x float> %x0, %x1294 %t1 = fmul reassoc nsz <4 x float> %x2, %t0295 %t2 = fmul reassoc nsz <4 x float> %x3, %t1296 ret <4 x float> %t2297}298 299; Verify that SSE and AVX 128-bit vector double-precision multiplies are reassociated.300 301define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {302; SSE-LABEL: reassociate_muls_v2f64:303; SSE: # %bb.0:304; SSE-NEXT: addpd %xmm1, %xmm0305; SSE-NEXT: mulpd %xmm3, %xmm2306; SSE-NEXT: mulpd %xmm2, %xmm0307; SSE-NEXT: retq308;309; AVX-LABEL: reassociate_muls_v2f64:310; AVX: # %bb.0:311; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0312; AVX-NEXT: vmulpd %xmm2, %xmm3, %xmm1313; AVX-NEXT: vmulpd %xmm0, %xmm1, %xmm0314; AVX-NEXT: retq315 %t0 = fadd reassoc nsz <2 x double> %x0, %x1316 %t1 = fmul reassoc nsz <2 x double> %x2, %t0317 %t2 = fmul reassoc nsz <2 x double> %x3, %t1318 ret <2 x double> %t2319}320 321; Verify that AVX 256-bit vector single-precision adds are reassociated.322 323define <8 x float> @reassociate_adds_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {324; SSE-LABEL: reassociate_adds_v8f32:325; SSE: # %bb.0:326; SSE-NEXT: mulps %xmm2, %xmm0327; SSE-NEXT: mulps %xmm3, %xmm1328; SSE-NEXT: addps %xmm6, %xmm4329; SSE-NEXT: addps %xmm4, %xmm0330; SSE-NEXT: addps %xmm7, %xmm5331; SSE-NEXT: addps %xmm5, %xmm1332; SSE-NEXT: retq333;334; AVX1-LABEL: reassociate_adds_v8f32:335; AVX1: # %bb.0:336; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0337; AVX1-NEXT: vaddps %ymm2, %ymm3, %ymm1338; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0339; AVX1-NEXT: retq340;341; AVX512-LABEL: reassociate_adds_v8f32:342; AVX512: # %bb.0:343; AVX512-NEXT: vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2344; AVX512-NEXT: vaddps %ymm0, %ymm3, %ymm0345; AVX512-NEXT: retq346 %t0 = fmul contract reassoc nsz <8 x float> %x0, %x1347 %t1 = fadd contract reassoc nsz <8 x float> %x2, %t0348 %t2 = fadd reassoc nsz <8 x float> %x3, %t1349 ret <8 x float> %t2350}351 352; Verify that AVX 256-bit vector double-precision adds are reassociated.353 354define <4 x double> @reassociate_adds_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {355; SSE-LABEL: reassociate_adds_v4f64:356; SSE: # %bb.0:357; SSE-NEXT: mulpd %xmm2, %xmm0358; SSE-NEXT: mulpd %xmm3, %xmm1359; SSE-NEXT: addpd %xmm6, %xmm4360; SSE-NEXT: addpd %xmm4, %xmm0361; SSE-NEXT: addpd %xmm7, %xmm5362; SSE-NEXT: addpd %xmm5, %xmm1363; SSE-NEXT: retq364;365; AVX1-LABEL: reassociate_adds_v4f64:366; AVX1: # %bb.0:367; AVX1-NEXT: vmulpd %ymm1, %ymm0, %ymm0368; AVX1-NEXT: vaddpd %ymm2, %ymm3, %ymm1369; AVX1-NEXT: vaddpd %ymm0, %ymm1, %ymm0370; AVX1-NEXT: retq371;372; AVX512-LABEL: reassociate_adds_v4f64:373; AVX512: # %bb.0:374; AVX512-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2375; AVX512-NEXT: vaddpd %ymm0, %ymm3, %ymm0376; AVX512-NEXT: retq377 %t0 = fmul contract reassoc nsz <4 x double> %x0, %x1378 %t1 = fadd contract reassoc nsz <4 x double> %x2, %t0379 %t2 = fadd reassoc nsz <4 x double> %x3, %t1380 ret <4 x double> %t2381}382 383; Verify that AVX 256-bit vector single-precision multiplies are reassociated.384 385define <8 x float> @reassociate_muls_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {386; SSE-LABEL: reassociate_muls_v8f32:387; SSE: # %bb.0:388; SSE-NEXT: addps %xmm2, %xmm0389; SSE-NEXT: addps %xmm3, %xmm1390; SSE-NEXT: mulps %xmm6, %xmm4391; SSE-NEXT: mulps %xmm4, %xmm0392; SSE-NEXT: mulps %xmm7, %xmm5393; SSE-NEXT: mulps %xmm5, %xmm1394; SSE-NEXT: retq395;396; AVX-LABEL: reassociate_muls_v8f32:397; AVX: # %bb.0:398; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0399; AVX-NEXT: vmulps %ymm2, %ymm3, %ymm1400; AVX-NEXT: vmulps %ymm0, %ymm1, %ymm0401; AVX-NEXT: retq402 %t0 = fadd reassoc nsz <8 x float> %x0, %x1403 %t1 = fmul reassoc nsz <8 x float> %x2, %t0404 %t2 = fmul reassoc nsz <8 x float> %x3, %t1405 ret <8 x float> %t2406}407 408; Verify that AVX 256-bit vector double-precision multiplies are reassociated.409 410define <4 x double> @reassociate_muls_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {411; SSE-LABEL: reassociate_muls_v4f64:412; SSE: # %bb.0:413; SSE-NEXT: addpd %xmm2, %xmm0414; SSE-NEXT: addpd %xmm3, %xmm1415; SSE-NEXT: mulpd %xmm6, %xmm4416; SSE-NEXT: mulpd %xmm4, %xmm0417; SSE-NEXT: mulpd %xmm7, %xmm5418; SSE-NEXT: mulpd %xmm5, %xmm1419; SSE-NEXT: retq420;421; AVX-LABEL: reassociate_muls_v4f64:422; AVX: # %bb.0:423; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0424; AVX-NEXT: vmulpd %ymm2, %ymm3, %ymm1425; AVX-NEXT: vmulpd %ymm0, %ymm1, %ymm0426; AVX-NEXT: retq427 %t0 = fadd reassoc nsz <4 x double> %x0, %x1428 %t1 = fmul reassoc nsz <4 x double> %x2, %t0429 %t2 = fmul reassoc nsz <4 x double> %x3, %t1430 ret <4 x double> %t2431}432 433; Verify that AVX512 512-bit vector single-precision adds are reassociated.434 435define <16 x float> @reassociate_adds_v16f32(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, <16 x float> %x3) {436; SSE-LABEL: reassociate_adds_v16f32:437; SSE: # %bb.0:438; SSE-NEXT: mulps %xmm4, %xmm0439; SSE-NEXT: mulps %xmm5, %xmm1440; SSE-NEXT: mulps %xmm6, %xmm2441; SSE-NEXT: mulps %xmm7, %xmm3442; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm3443; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm2444; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm1445; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm0446; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm0447; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm1448; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm2449; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm3450; SSE-NEXT: retq451;452; AVX1-LABEL: reassociate_adds_v16f32:453; AVX1: # %bb.0:454; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0455; AVX1-NEXT: vmulps %ymm3, %ymm1, %ymm1456; AVX1-NEXT: vaddps %ymm4, %ymm6, %ymm2457; AVX1-NEXT: vaddps %ymm0, %ymm2, %ymm0458; AVX1-NEXT: vaddps %ymm5, %ymm7, %ymm2459; AVX1-NEXT: vaddps %ymm1, %ymm2, %ymm1460; AVX1-NEXT: retq461;462; AVX512-LABEL: reassociate_adds_v16f32:463; AVX512: # %bb.0:464; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2465; AVX512-NEXT: vaddps %zmm0, %zmm3, %zmm0466; AVX512-NEXT: retq467 %t0 = fmul contract reassoc nsz <16 x float> %x0, %x1468 %t1 = fadd contract reassoc nsz <16 x float> %x2, %t0469 %t2 = fadd reassoc nsz <16 x float> %x3, %t1470 ret <16 x float> %t2471}472 473; Verify that AVX512 512-bit vector double-precision adds are reassociated.474 475define <8 x double> @reassociate_adds_v8f64(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, <8 x double> %x3) {476; SSE-LABEL: reassociate_adds_v8f64:477; SSE: # %bb.0:478; SSE-NEXT: mulpd %xmm4, %xmm0479; SSE-NEXT: mulpd %xmm5, %xmm1480; SSE-NEXT: mulpd %xmm6, %xmm2481; SSE-NEXT: mulpd %xmm7, %xmm3482; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm3483; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm2484; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm1485; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm0486; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm0487; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm1488; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm2489; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm3490; SSE-NEXT: retq491;492; AVX1-LABEL: reassociate_adds_v8f64:493; AVX1: # %bb.0:494; AVX1-NEXT: vmulpd %ymm2, %ymm0, %ymm0495; AVX1-NEXT: vmulpd %ymm3, %ymm1, %ymm1496; AVX1-NEXT: vaddpd %ymm4, %ymm6, %ymm2497; AVX1-NEXT: vaddpd %ymm0, %ymm2, %ymm0498; AVX1-NEXT: vaddpd %ymm5, %ymm7, %ymm2499; AVX1-NEXT: vaddpd %ymm1, %ymm2, %ymm1500; AVX1-NEXT: retq501;502; AVX512-LABEL: reassociate_adds_v8f64:503; AVX512: # %bb.0:504; AVX512-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2505; AVX512-NEXT: vaddpd %zmm0, %zmm3, %zmm0506; AVX512-NEXT: retq507 %t0 = fmul contract reassoc nsz <8 x double> %x0, %x1508 %t1 = fadd contract reassoc nsz <8 x double> %x2, %t0509 %t2 = fadd reassoc nsz <8 x double> %x3, %t1510 ret <8 x double> %t2511}512 513; Verify that AVX512 512-bit vector single-precision multiplies are reassociated.514 515define <16 x float> @reassociate_muls_v16f32(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, <16 x float> %x3) {516; SSE-LABEL: reassociate_muls_v16f32:517; SSE: # %bb.0:518; SSE-NEXT: addps %xmm4, %xmm0519; SSE-NEXT: addps %xmm5, %xmm1520; SSE-NEXT: addps %xmm6, %xmm2521; SSE-NEXT: addps %xmm7, %xmm3522; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm3523; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm2524; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm1525; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm0526; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm0527; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm1528; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm2529; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm3530; SSE-NEXT: retq531;532; AVX1-LABEL: reassociate_muls_v16f32:533; AVX1: # %bb.0:534; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0535; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1536; AVX1-NEXT: vmulps %ymm4, %ymm6, %ymm2537; AVX1-NEXT: vmulps %ymm0, %ymm2, %ymm0538; AVX1-NEXT: vmulps %ymm5, %ymm7, %ymm2539; AVX1-NEXT: vmulps %ymm1, %ymm2, %ymm1540; AVX1-NEXT: retq541;542; AVX512-LABEL: reassociate_muls_v16f32:543; AVX512: # %bb.0:544; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0545; AVX512-NEXT: vmulps %zmm2, %zmm3, %zmm1546; AVX512-NEXT: vmulps %zmm0, %zmm1, %zmm0547; AVX512-NEXT: retq548 %t0 = fadd reassoc nsz <16 x float> %x0, %x1549 %t1 = fmul reassoc nsz <16 x float> %x2, %t0550 %t2 = fmul reassoc nsz <16 x float> %x3, %t1551 ret <16 x float> %t2552}553 554; Verify that AVX512 512-bit vector double-precision multiplies are reassociated.555 556define <8 x double> @reassociate_muls_v8f64(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, <8 x double> %x3) {557; SSE-LABEL: reassociate_muls_v8f64:558; SSE: # %bb.0:559; SSE-NEXT: addpd %xmm4, %xmm0560; SSE-NEXT: addpd %xmm5, %xmm1561; SSE-NEXT: addpd %xmm6, %xmm2562; SSE-NEXT: addpd %xmm7, %xmm3563; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm3564; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm2565; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm1566; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm0567; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm0568; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm1569; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm2570; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm3571; SSE-NEXT: retq572;573; AVX1-LABEL: reassociate_muls_v8f64:574; AVX1: # %bb.0:575; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0576; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1577; AVX1-NEXT: vmulpd %ymm4, %ymm6, %ymm2578; AVX1-NEXT: vmulpd %ymm0, %ymm2, %ymm0579; AVX1-NEXT: vmulpd %ymm5, %ymm7, %ymm2580; AVX1-NEXT: vmulpd %ymm1, %ymm2, %ymm1581; AVX1-NEXT: retq582;583; AVX512-LABEL: reassociate_muls_v8f64:584; AVX512: # %bb.0:585; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0586; AVX512-NEXT: vmulpd %zmm2, %zmm3, %zmm1587; AVX512-NEXT: vmulpd %zmm0, %zmm1, %zmm0588; AVX512-NEXT: retq589 %t0 = fadd reassoc nsz <8 x double> %x0, %x1590 %t1 = fmul reassoc nsz <8 x double> %x2, %t0591 %t2 = fmul reassoc nsz <8 x double> %x3, %t1592 ret <8 x double> %t2593}594 595; Verify that SSE and AVX scalar single-precision minimum ops are reassociated.596 597define float @reassociate_mins_single(float %x0, float %x1, float %x2, float %x3) {598; SSE-LABEL: reassociate_mins_single:599; SSE: # %bb.0:600; SSE-NEXT: divss %xmm1, %xmm0601; SSE-NEXT: minss %xmm3, %xmm2602; SSE-NEXT: minss %xmm2, %xmm0603; SSE-NEXT: retq604;605; AVX-LABEL: reassociate_mins_single:606; AVX: # %bb.0:607; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0608; AVX-NEXT: vminss %xmm2, %xmm3, %xmm1609; AVX-NEXT: vminss %xmm0, %xmm1, %xmm0610; AVX-NEXT: retq611 %t0 = fdiv float %x0, %x1612 %cmp1 = fcmp olt float %x2, %t0613 %sel1 = select i1 %cmp1, float %x2, float %t0614 %cmp2 = fcmp olt float %x3, %sel1615 %sel2 = select i1 %cmp2, float %x3, float %sel1616 ret float %sel2617}618 619; Verify that SSE and AVX scalar single-precision maximum ops are reassociated.620 621define float @reassociate_maxs_single(float %x0, float %x1, float %x2, float %x3) {622; SSE-LABEL: reassociate_maxs_single:623; SSE: # %bb.0:624; SSE-NEXT: divss %xmm1, %xmm0625; SSE-NEXT: maxss %xmm3, %xmm2626; SSE-NEXT: maxss %xmm2, %xmm0627; SSE-NEXT: retq628;629; AVX-LABEL: reassociate_maxs_single:630; AVX: # %bb.0:631; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0632; AVX-NEXT: vmaxss %xmm2, %xmm3, %xmm1633; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm0634; AVX-NEXT: retq635 %t0 = fdiv float %x0, %x1636 %cmp1 = fcmp ogt float %x2, %t0637 %sel1 = select i1 %cmp1, float %x2, float %t0638 %cmp2 = fcmp ogt float %x3, %sel1639 %sel2 = select i1 %cmp2, float %x3, float %sel1640 ret float %sel2641}642 643; Verify that SSE and AVX scalar double-precision minimum ops are reassociated.644 645define double @reassociate_mins_double(double %x0, double %x1, double %x2, double %x3) {646; SSE-LABEL: reassociate_mins_double:647; SSE: # %bb.0:648; SSE-NEXT: divsd %xmm1, %xmm0649; SSE-NEXT: minsd %xmm3, %xmm2650; SSE-NEXT: minsd %xmm2, %xmm0651; SSE-NEXT: retq652;653; AVX-LABEL: reassociate_mins_double:654; AVX: # %bb.0:655; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0656; AVX-NEXT: vminsd %xmm2, %xmm3, %xmm1657; AVX-NEXT: vminsd %xmm0, %xmm1, %xmm0658; AVX-NEXT: retq659 %t0 = fdiv double %x0, %x1660 %cmp1 = fcmp olt double %x2, %t0661 %sel1 = select i1 %cmp1, double %x2, double %t0662 %cmp2 = fcmp olt double %x3, %sel1663 %sel2 = select i1 %cmp2, double %x3, double %sel1664 ret double %sel2665}666 667; Verify that SSE and AVX scalar double-precision maximum ops are reassociated.668 669define double @reassociate_maxs_double(double %x0, double %x1, double %x2, double %x3) {670; SSE-LABEL: reassociate_maxs_double:671; SSE: # %bb.0:672; SSE-NEXT: divsd %xmm1, %xmm0673; SSE-NEXT: maxsd %xmm3, %xmm2674; SSE-NEXT: maxsd %xmm2, %xmm0675; SSE-NEXT: retq676;677; AVX-LABEL: reassociate_maxs_double:678; AVX: # %bb.0:679; AVX-NEXT: vdivsd %xmm1, %xmm0, %xmm0680; AVX-NEXT: vmaxsd %xmm2, %xmm3, %xmm1681; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm0682; AVX-NEXT: retq683 %t0 = fdiv double %x0, %x1684 %cmp1 = fcmp ogt double %x2, %t0685 %sel1 = select i1 %cmp1, double %x2, double %t0686 %cmp2 = fcmp ogt double %x3, %sel1687 %sel2 = select i1 %cmp2, double %x3, double %sel1688 ret double %sel2689}690 691; Verify that SSE and AVX 128-bit vector single-precision minimum ops are reassociated.692 693define <4 x float> @reassociate_mins_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {694; SSE-LABEL: reassociate_mins_v4f32:695; SSE: # %bb.0:696; SSE-NEXT: addps %xmm1, %xmm0697; SSE-NEXT: minps %xmm3, %xmm2698; SSE-NEXT: minps %xmm2, %xmm0699; SSE-NEXT: retq700;701; AVX-LABEL: reassociate_mins_v4f32:702; AVX: # %bb.0:703; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0704; AVX-NEXT: vminps %xmm2, %xmm3, %xmm1705; AVX-NEXT: vminps %xmm0, %xmm1, %xmm0706; AVX-NEXT: retq707 %t0 = fadd <4 x float> %x0, %x1708 %cmp1 = fcmp olt <4 x float> %x2, %t0709 %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0710 %cmp2 = fcmp olt <4 x float> %x3, %sel1711 %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1712 ret <4 x float> %sel2713}714 715; Verify that SSE and AVX 128-bit vector single-precision maximum ops are reassociated.716 717define <4 x float> @reassociate_maxs_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {718; SSE-LABEL: reassociate_maxs_v4f32:719; SSE: # %bb.0:720; SSE-NEXT: addps %xmm1, %xmm0721; SSE-NEXT: maxps %xmm3, %xmm2722; SSE-NEXT: maxps %xmm2, %xmm0723; SSE-NEXT: retq724;725; AVX-LABEL: reassociate_maxs_v4f32:726; AVX: # %bb.0:727; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0728; AVX-NEXT: vmaxps %xmm2, %xmm3, %xmm1729; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0730; AVX-NEXT: retq731 %t0 = fadd <4 x float> %x0, %x1732 %cmp1 = fcmp ogt <4 x float> %x2, %t0733 %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0734 %cmp2 = fcmp ogt <4 x float> %x3, %sel1735 %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1736 ret <4 x float> %sel2737}738 739; Verify that SSE and AVX 128-bit vector double-precision minimum ops are reassociated.740 741define <2 x double> @reassociate_mins_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {742; SSE-LABEL: reassociate_mins_v2f64:743; SSE: # %bb.0:744; SSE-NEXT: addpd %xmm1, %xmm0745; SSE-NEXT: minpd %xmm3, %xmm2746; SSE-NEXT: minpd %xmm2, %xmm0747; SSE-NEXT: retq748;749; AVX-LABEL: reassociate_mins_v2f64:750; AVX: # %bb.0:751; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0752; AVX-NEXT: vminpd %xmm2, %xmm3, %xmm1753; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0754; AVX-NEXT: retq755 %t0 = fadd <2 x double> %x0, %x1756 %cmp1 = fcmp olt <2 x double> %x2, %t0757 %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0758 %cmp2 = fcmp olt <2 x double> %x3, %sel1759 %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1760 ret <2 x double> %sel2761}762 763; Verify that SSE and AVX 128-bit vector double-precision maximum ops are reassociated.764 765define <2 x double> @reassociate_maxs_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {766; SSE-LABEL: reassociate_maxs_v2f64:767; SSE: # %bb.0:768; SSE-NEXT: addpd %xmm1, %xmm0769; SSE-NEXT: maxpd %xmm3, %xmm2770; SSE-NEXT: maxpd %xmm2, %xmm0771; SSE-NEXT: retq772;773; AVX-LABEL: reassociate_maxs_v2f64:774; AVX: # %bb.0:775; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0776; AVX-NEXT: vmaxpd %xmm2, %xmm3, %xmm1777; AVX-NEXT: vmaxpd %xmm0, %xmm1, %xmm0778; AVX-NEXT: retq779 %t0 = fadd <2 x double> %x0, %x1780 %cmp1 = fcmp ogt <2 x double> %x2, %t0781 %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0782 %cmp2 = fcmp ogt <2 x double> %x3, %sel1783 %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1784 ret <2 x double> %sel2785}786 787; Verify that AVX 256-bit vector single-precision minimum ops are reassociated.788 789define <8 x float> @reassociate_mins_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {790; SSE-LABEL: reassociate_mins_v8f32:791; SSE: # %bb.0:792; SSE-NEXT: addps %xmm2, %xmm0793; SSE-NEXT: addps %xmm3, %xmm1794; SSE-NEXT: minps %xmm6, %xmm4795; SSE-NEXT: minps %xmm4, %xmm0796; SSE-NEXT: minps %xmm7, %xmm5797; SSE-NEXT: minps %xmm5, %xmm1798; SSE-NEXT: retq799;800; AVX-LABEL: reassociate_mins_v8f32:801; AVX: # %bb.0:802; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0803; AVX-NEXT: vminps %ymm2, %ymm3, %ymm1804; AVX-NEXT: vminps %ymm0, %ymm1, %ymm0805; AVX-NEXT: retq806 %t0 = fadd <8 x float> %x0, %x1807 %cmp1 = fcmp olt <8 x float> %x2, %t0808 %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0809 %cmp2 = fcmp olt <8 x float> %x3, %sel1810 %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1811 ret <8 x float> %sel2812}813 814; Verify that AVX 256-bit vector single-precision maximum ops are reassociated.815 816define <8 x float> @reassociate_maxs_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {817; SSE-LABEL: reassociate_maxs_v8f32:818; SSE: # %bb.0:819; SSE-NEXT: addps %xmm2, %xmm0820; SSE-NEXT: addps %xmm3, %xmm1821; SSE-NEXT: maxps %xmm6, %xmm4822; SSE-NEXT: maxps %xmm4, %xmm0823; SSE-NEXT: maxps %xmm7, %xmm5824; SSE-NEXT: maxps %xmm5, %xmm1825; SSE-NEXT: retq826;827; AVX-LABEL: reassociate_maxs_v8f32:828; AVX: # %bb.0:829; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0830; AVX-NEXT: vmaxps %ymm2, %ymm3, %ymm1831; AVX-NEXT: vmaxps %ymm0, %ymm1, %ymm0832; AVX-NEXT: retq833 %t0 = fadd <8 x float> %x0, %x1834 %cmp1 = fcmp ogt <8 x float> %x2, %t0835 %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0836 %cmp2 = fcmp ogt <8 x float> %x3, %sel1837 %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1838 ret <8 x float> %sel2839}840 841; Verify that AVX 256-bit vector double-precision minimum ops are reassociated.842 843define <4 x double> @reassociate_mins_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {844; SSE-LABEL: reassociate_mins_v4f64:845; SSE: # %bb.0:846; SSE-NEXT: addpd %xmm2, %xmm0847; SSE-NEXT: addpd %xmm3, %xmm1848; SSE-NEXT: minpd %xmm6, %xmm4849; SSE-NEXT: minpd %xmm4, %xmm0850; SSE-NEXT: minpd %xmm7, %xmm5851; SSE-NEXT: minpd %xmm5, %xmm1852; SSE-NEXT: retq853;854; AVX-LABEL: reassociate_mins_v4f64:855; AVX: # %bb.0:856; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0857; AVX-NEXT: vminpd %ymm2, %ymm3, %ymm1858; AVX-NEXT: vminpd %ymm0, %ymm1, %ymm0859; AVX-NEXT: retq860 %t0 = fadd <4 x double> %x0, %x1861 %cmp1 = fcmp olt <4 x double> %x2, %t0862 %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0863 %cmp2 = fcmp olt <4 x double> %x3, %sel1864 %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1865 ret <4 x double> %sel2866}867 868; Verify that AVX 256-bit vector double-precision maximum ops are reassociated.869 870define <4 x double> @reassociate_maxs_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {871; SSE-LABEL: reassociate_maxs_v4f64:872; SSE: # %bb.0:873; SSE-NEXT: addpd %xmm2, %xmm0874; SSE-NEXT: addpd %xmm3, %xmm1875; SSE-NEXT: maxpd %xmm6, %xmm4876; SSE-NEXT: maxpd %xmm4, %xmm0877; SSE-NEXT: maxpd %xmm7, %xmm5878; SSE-NEXT: maxpd %xmm5, %xmm1879; SSE-NEXT: retq880;881; AVX-LABEL: reassociate_maxs_v4f64:882; AVX: # %bb.0:883; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0884; AVX-NEXT: vmaxpd %ymm2, %ymm3, %ymm1885; AVX-NEXT: vmaxpd %ymm0, %ymm1, %ymm0886; AVX-NEXT: retq887 %t0 = fadd <4 x double> %x0, %x1888 %cmp1 = fcmp ogt <4 x double> %x2, %t0889 %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0890 %cmp2 = fcmp ogt <4 x double> %x3, %sel1891 %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1892 ret <4 x double> %sel2893}894 895; Verify that AVX512 512-bit vector single-precision minimum ops are reassociated.896 897define <16 x float> @reassociate_mins_v16f32(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, <16 x float> %x3) {898; SSE-LABEL: reassociate_mins_v16f32:899; SSE: # %bb.0:900; SSE-NEXT: addps %xmm4, %xmm0901; SSE-NEXT: addps %xmm5, %xmm1902; SSE-NEXT: addps %xmm6, %xmm2903; SSE-NEXT: addps %xmm7, %xmm3904; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm3905; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm2906; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm1907; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm0908; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm0909; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm1910; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm2911; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm3912; SSE-NEXT: retq913;914; AVX1-LABEL: reassociate_mins_v16f32:915; AVX1: # %bb.0:916; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0917; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1918; AVX1-NEXT: vminps %ymm4, %ymm6, %ymm2919; AVX1-NEXT: vminps %ymm0, %ymm2, %ymm0920; AVX1-NEXT: vminps %ymm5, %ymm7, %ymm2921; AVX1-NEXT: vminps %ymm1, %ymm2, %ymm1922; AVX1-NEXT: retq923;924; AVX512-LABEL: reassociate_mins_v16f32:925; AVX512: # %bb.0:926; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0927; AVX512-NEXT: vminps %zmm2, %zmm3, %zmm1928; AVX512-NEXT: vminps %zmm0, %zmm1, %zmm0929; AVX512-NEXT: retq930 %t0 = fadd <16 x float> %x0, %x1931 %cmp1 = fcmp olt <16 x float> %x2, %t0932 %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0933 %cmp2 = fcmp olt <16 x float> %x3, %sel1934 %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1935 ret <16 x float> %sel2936}937 938; Verify that AVX512 512-bit vector single-precision maximum ops are reassociated.939 940define <16 x float> @reassociate_maxs_v16f32(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, <16 x float> %x3) {941; SSE-LABEL: reassociate_maxs_v16f32:942; SSE: # %bb.0:943; SSE-NEXT: addps %xmm4, %xmm0944; SSE-NEXT: addps %xmm5, %xmm1945; SSE-NEXT: addps %xmm6, %xmm2946; SSE-NEXT: addps %xmm7, %xmm3947; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm3948; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm2949; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm1950; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm0951; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm0952; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm1953; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm2954; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm3955; SSE-NEXT: retq956;957; AVX1-LABEL: reassociate_maxs_v16f32:958; AVX1: # %bb.0:959; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0960; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1961; AVX1-NEXT: vmaxps %ymm4, %ymm6, %ymm2962; AVX1-NEXT: vmaxps %ymm0, %ymm2, %ymm0963; AVX1-NEXT: vmaxps %ymm5, %ymm7, %ymm2964; AVX1-NEXT: vmaxps %ymm1, %ymm2, %ymm1965; AVX1-NEXT: retq966;967; AVX512-LABEL: reassociate_maxs_v16f32:968; AVX512: # %bb.0:969; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0970; AVX512-NEXT: vmaxps %zmm2, %zmm3, %zmm1971; AVX512-NEXT: vmaxps %zmm0, %zmm1, %zmm0972; AVX512-NEXT: retq973 %t0 = fadd <16 x float> %x0, %x1974 %cmp1 = fcmp ogt <16 x float> %x2, %t0975 %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0976 %cmp2 = fcmp ogt <16 x float> %x3, %sel1977 %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1978 ret <16 x float> %sel2979}980 981; Verify that AVX512 512-bit vector double-precision minimum ops are reassociated.982 983define <8 x double> @reassociate_mins_v8f64(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, <8 x double> %x3) {984; SSE-LABEL: reassociate_mins_v8f64:985; SSE: # %bb.0:986; SSE-NEXT: addpd %xmm4, %xmm0987; SSE-NEXT: addpd %xmm5, %xmm1988; SSE-NEXT: addpd %xmm6, %xmm2989; SSE-NEXT: addpd %xmm7, %xmm3990; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm3991; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm2992; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm1993; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm0994; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm0995; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm1996; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm2997; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm3998; SSE-NEXT: retq999;1000; AVX1-LABEL: reassociate_mins_v8f64:1001; AVX1: # %bb.0:1002; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm01003; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm11004; AVX1-NEXT: vminpd %ymm4, %ymm6, %ymm21005; AVX1-NEXT: vminpd %ymm0, %ymm2, %ymm01006; AVX1-NEXT: vminpd %ymm5, %ymm7, %ymm21007; AVX1-NEXT: vminpd %ymm1, %ymm2, %ymm11008; AVX1-NEXT: retq1009;1010; AVX512-LABEL: reassociate_mins_v8f64:1011; AVX512: # %bb.0:1012; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm01013; AVX512-NEXT: vminpd %zmm2, %zmm3, %zmm11014; AVX512-NEXT: vminpd %zmm0, %zmm1, %zmm01015; AVX512-NEXT: retq1016 %t0 = fadd <8 x double> %x0, %x11017 %cmp1 = fcmp olt <8 x double> %x2, %t01018 %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t01019 %cmp2 = fcmp olt <8 x double> %x3, %sel11020 %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel11021 ret <8 x double> %sel21022}1023 1024; Verify that AVX512 512-bit vector double-precision maximum ops are reassociated.1025 1026define <8 x double> @reassociate_maxs_v8f64(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, <8 x double> %x3) {1027; SSE-LABEL: reassociate_maxs_v8f64:1028; SSE: # %bb.0:1029; SSE-NEXT: addpd %xmm4, %xmm01030; SSE-NEXT: addpd %xmm5, %xmm11031; SSE-NEXT: addpd %xmm6, %xmm21032; SSE-NEXT: addpd %xmm7, %xmm31033; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm31034; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm21035; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm11036; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm01037; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm01038; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm11039; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm21040; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm31041; SSE-NEXT: retq1042;1043; AVX1-LABEL: reassociate_maxs_v8f64:1044; AVX1: # %bb.0:1045; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm01046; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm11047; AVX1-NEXT: vmaxpd %ymm4, %ymm6, %ymm21048; AVX1-NEXT: vmaxpd %ymm0, %ymm2, %ymm01049; AVX1-NEXT: vmaxpd %ymm5, %ymm7, %ymm21050; AVX1-NEXT: vmaxpd %ymm1, %ymm2, %ymm11051; AVX1-NEXT: retq1052;1053; AVX512-LABEL: reassociate_maxs_v8f64:1054; AVX512: # %bb.0:1055; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm01056; AVX512-NEXT: vmaxpd %zmm2, %zmm3, %zmm11057; AVX512-NEXT: vmaxpd %zmm0, %zmm1, %zmm01058; AVX512-NEXT: retq1059 %t0 = fadd <8 x double> %x0, %x11060 %cmp1 = fcmp ogt <8 x double> %x2, %t01061 %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t01062 %cmp2 = fcmp ogt <8 x double> %x3, %sel11063 %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel11064 ret <8 x double> %sel21065}1066 1067; PR25016: https://llvm.org/bugs/show_bug.cgi?id=250161068; Verify that reassociation is not happening needlessly or wrongly.1069 1070declare double @bar()1071 1072define double @reassociate_adds_from_calls() {1073; SSE-LABEL: reassociate_adds_from_calls:1074; SSE: # %bb.0:1075; SSE-NEXT: subq $24, %rsp1076; SSE-NEXT: .cfi_def_cfa_offset 321077; SSE-NEXT: callq bar@PLT1078; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1079; SSE-NEXT: callq bar@PLT1080; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1081; SSE-NEXT: callq bar@PLT1082; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill1083; SSE-NEXT: callq bar@PLT1084; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload1085; SSE-NEXT: # xmm1 = mem[0],zero1086; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload1087; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload1088; SSE-NEXT: addsd %xmm1, %xmm01089; SSE-NEXT: addq $24, %rsp1090; SSE-NEXT: .cfi_def_cfa_offset 81091; SSE-NEXT: retq1092;1093; AVX-LABEL: reassociate_adds_from_calls:1094; AVX: # %bb.0:1095; AVX-NEXT: subq $24, %rsp1096; AVX-NEXT: .cfi_def_cfa_offset 321097; AVX-NEXT: callq bar@PLT1098; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1099; AVX-NEXT: callq bar@PLT1100; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1101; AVX-NEXT: callq bar@PLT1102; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill1103; AVX-NEXT: callq bar@PLT1104; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload1105; AVX-NEXT: # xmm1 = mem[0],zero1106; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload1107; AVX-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload1108; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm01109; AVX-NEXT: addq $24, %rsp1110; AVX-NEXT: .cfi_def_cfa_offset 81111; AVX-NEXT: retq1112 1113 %x0 = call double @bar()1114 %x1 = call double @bar()1115 %x2 = call double @bar()1116 %x3 = call double @bar()1117 %t0 = fadd reassoc nsz double %x0, %x11118 %t1 = fadd reassoc nsz double %t0, %x21119 %t2 = fadd reassoc nsz double %t1, %x31120 ret double %t21121}1122 1123define double @already_reassociated() {1124; SSE-LABEL: already_reassociated:1125; SSE: # %bb.0:1126; SSE-NEXT: subq $24, %rsp1127; SSE-NEXT: .cfi_def_cfa_offset 321128; SSE-NEXT: callq bar@PLT1129; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1130; SSE-NEXT: callq bar@PLT1131; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1132; SSE-NEXT: callq bar@PLT1133; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill1134; SSE-NEXT: callq bar@PLT1135; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload1136; SSE-NEXT: # xmm1 = mem[0],zero1137; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload1138; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload1139; SSE-NEXT: addsd %xmm1, %xmm01140; SSE-NEXT: addq $24, %rsp1141; SSE-NEXT: .cfi_def_cfa_offset 81142; SSE-NEXT: retq1143;1144; AVX-LABEL: already_reassociated:1145; AVX: # %bb.0:1146; AVX-NEXT: subq $24, %rsp1147; AVX-NEXT: .cfi_def_cfa_offset 321148; AVX-NEXT: callq bar@PLT1149; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1150; AVX-NEXT: callq bar@PLT1151; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill1152; AVX-NEXT: callq bar@PLT1153; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill1154; AVX-NEXT: callq bar@PLT1155; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload1156; AVX-NEXT: # xmm1 = mem[0],zero1157; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload1158; AVX-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload1159; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm01160; AVX-NEXT: addq $24, %rsp1161; AVX-NEXT: .cfi_def_cfa_offset 81162; AVX-NEXT: retq1163 1164 %x0 = call double @bar()1165 %x1 = call double @bar()1166 %x2 = call double @bar()1167 %x3 = call double @bar()1168 %t0 = fadd reassoc nsz double %x0, %x11169 %t1 = fadd reassoc nsz double %x2, %x31170 %t2 = fadd reassoc nsz double %t0, %t11171 ret double %t21172}1173 1174