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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=machine-sink %s -o - | FileCheck %s3# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -run-pass=mir-debugify,machine-sink,mir-strip-debug %s -o - | FileCheck %s4 5# RUN: llc -mtriple=x86_64 -machine-sink-load-instrs-threshold=2 -passes=machine-sink %s -o - | FileCheck %s6# TODO: add test with mir-debugify once it is ported7 8# Verify that machine-sink pass is debug invariant wrt to given input. Since9# the pass examines MemOperands the IR is required for the original bug to10# trigger.11 12--- |13 @e = global i32 0, align 114 @d = global i32 0, align 115 @f = global i32 0, align 116 @g = global i32 0, align 117 18 define i32 @l() {19 entry:20 br label %for.body21 22 for.body: ; preds = %h.exit, %entry23 %cmp = phi i1 [ true, %entry ], [ false, %h.exit ]24 %0 = load i32, ptr @d, align 125 %tobool61.not.i = icmp eq i32 %0, 026 %e.promoted44.i = load i32, ptr @e, align 127 br i1 %tobool61.not.i, label %h.exit, label %for.cond13.preheader.preheader.i28 29 for.cond13.preheader.preheader.i: ; preds = %for.body30 %1 = load i32, ptr @f, align 131 store i32 %1, ptr @g, align 132 br label %h.exit33 34 h.exit: ; preds = %for.cond13.preheader.preheader.i, %for.body35 %.us-phi50.i = or i32 %e.promoted44.i, 436 store i32 %.us-phi50.i, ptr @e, align 137 br i1 %cmp, label %for.body, label %for.end38 39 for.end: ; preds = %h.exit40 ret i32 undef41 }42...43---44name: l45alignment: 1646tracksRegLiveness: true47registers:48 - { id: 0, class: gr8 }49 - { id: 1, class: gr32 }50 - { id: 2, class: gr8 }51 - { id: 3, class: gr64 }52 - { id: 4, class: gr64 }53 - { id: 5, class: gr64 }54 - { id: 6, class: gr32 }55 - { id: 7, class: gr64 }56 - { id: 8, class: gr8 }57 - { id: 9, class: gr32 }58 - { id: 10, class: gr64 }59 - { id: 11, class: gr32 }60 - { id: 12, class: gr32 }61frameInfo:62 maxAlignment: 163machineFunctionInfo: {}64body: |65 ; CHECK-LABEL: name: l66 ; CHECK: bb.0.entry:67 ; CHECK-NEXT: successors: %bb.1(0x80000000)68 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 170 ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @d, $noreg :: (load (s64) from got)71 ; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @e, $noreg :: (load (s64) from got)72 ; CHECK-NEXT: [[MOV64rm2:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @f, $noreg :: (load (s64) from got)73 ; CHECK-NEXT: [[MOV64rm3:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @g, $noreg :: (load (s64) from got)74 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: bb.1.for.body:76 ; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.2(0x50000000)77 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr8 = PHI [[MOV8ri]], %bb.0, %8, %bb.379 ; CHECK-NEXT: CMP32mi [[MOV64rm]], 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (dereferenceable load (s32) from @d, align 1)80 ; CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags81 ; CHECK-NEXT: JMP_1 %bb.282 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: bb.2.for.cond13.preheader.preheader.i:84 ; CHECK-NEXT: successors: %bb.3(0x80000000)85 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[MOV64rm2]], 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @f, align 1)87 ; CHECK-NEXT: MOV32mr [[MOV64rm3]], 1, $noreg, 0, $noreg, killed [[MOV32rm]] :: (store (s32) into @g, align 1)88 ; CHECK-NEXT: {{ $}}89 ; CHECK-NEXT: bb.3.h.exit:90 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)91 ; CHECK-NEXT: {{ $}}92 ; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV64rm1]], 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @e, align 1)93 ; CHECK-NEXT: [[OR32ri8_:%[0-9]+]]:gr32 = OR32ri8 [[MOV32rm1]], 4, implicit-def dead $eflags94 ; CHECK-NEXT: MOV32mr [[MOV64rm1]], 1, $noreg, 0, $noreg, killed [[OR32ri8_]] :: (store (s32) into @e, align 1)95 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags96 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY [[MOV32r0_]].sub_8bit97 ; CHECK-NEXT: TEST8ri [[PHI]], 1, implicit-def $eflags98 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags99 ; CHECK-NEXT: JMP_1 %bb.4100 ; CHECK-NEXT: {{ $}}101 ; CHECK-NEXT: bb.4.for.end:102 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF103 ; CHECK-NEXT: $eax = COPY [[DEF]]104 ; CHECK-NEXT: RET 0, $eax105 bb.0.entry:106 %2:gr8 = MOV8ri 1107 %3:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @d, $noreg :: (load (s64) from got)108 %4:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @e, $noreg :: (load (s64) from got)109 %5:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @f, $noreg :: (load (s64) from got)110 %7:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @g, $noreg :: (load (s64) from got)111 112 bb.1.for.body:113 successors: %bb.3(0x30000000), %bb.2(0x50000000)114 115 %0:gr8 = PHI %2, %bb.0, %8, %bb.3116 CMP32mi %3, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (dereferenceable load (s32) from @d, align 1)117 %1:gr32 = MOV32rm %4, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @e, align 1)118 JCC_1 %bb.3, 4, implicit $eflags119 JMP_1 %bb.2120 121 bb.2.for.cond13.preheader.preheader.i:122 %6:gr32 = MOV32rm %5, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @f, align 1)123 MOV32mr %7, 1, $noreg, 0, $noreg, killed %6 :: (store (s32) into @g, align 1)124 125 bb.3.h.exit:126 successors: %bb.1(0x7c000000), %bb.4(0x04000000)127 128 %9:gr32 = OR32ri8 %1, 4, implicit-def dead $eflags129 MOV32mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s32) into @e, align 1)130 %11:gr32 = MOV32r0 implicit-def dead $eflags131 %8:gr8 = COPY %11.sub_8bit132 TEST8ri %0, 1, implicit-def $eflags133 JCC_1 %bb.1, 5, implicit $eflags134 JMP_1 %bb.4135 136 bb.4.for.end:137 %12:gr32 = IMPLICIT_DEF138 $eax = COPY %12139 RET 0, $eax140...141