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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse2,-sse4.2 | FileCheck %s --check-prefixes=GPR,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=sse4.2,-avx | FileCheck %s --check-prefixes=GPR,SSE44; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx,-avx512f | FileCheck %s --check-prefixes=GPR,AVX5; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512f | FileCheck %s --check-prefixes=GPR,AVX5126 7declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind8declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind9 10; /////////////////////////////////////////////////////////////////////////////11 12define void @memset_1(ptr %a, i8 %value) nounwind {13; GPR-LABEL: memset_1:14; GPR: # %bb.0:15; GPR-NEXT: movb %sil, (%rdi)16; GPR-NEXT: retq17 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 1, i1 0)18 ret void19}20 21define void @memset_2(ptr %a, i8 %value) nounwind {22; GPR-LABEL: memset_2:23; GPR: # %bb.0:24; GPR-NEXT: movzbl %sil, %eax25; GPR-NEXT: shll $8, %esi26; GPR-NEXT: orl %esi, %eax27; GPR-NEXT: movw %ax, (%rdi)28; GPR-NEXT: retq29 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 2, i1 0)30 ret void31}32 33define void @memset_4(ptr %a, i8 %value) nounwind {34; GPR-LABEL: memset_4:35; GPR: # %bb.0:36; GPR-NEXT: movzbl %sil, %eax37; GPR-NEXT: imull $16843009, %eax, %eax # imm = 0x101010138; GPR-NEXT: movl %eax, (%rdi)39; GPR-NEXT: retq40 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 4, i1 0)41 ret void42}43 44define void @memset_8(ptr %a, i8 %value) nounwind {45; GPR-LABEL: memset_8:46; GPR: # %bb.0:47; GPR-NEXT: movzbl %sil, %eax48; GPR-NEXT: movabsq $72340172838076673, %rcx # imm = 0x10101010101010149; GPR-NEXT: imulq %rax, %rcx50; GPR-NEXT: movq %rcx, (%rdi)51; GPR-NEXT: retq52 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 8, i1 0)53 ret void54}55 56define void @memset_16(ptr %a, i8 %value) nounwind {57; SSE2-LABEL: memset_16:58; SSE2: # %bb.0:59; SSE2-NEXT: movzbl %sil, %eax60; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x10101010101010161; SSE2-NEXT: imulq %rax, %rcx62; SSE2-NEXT: movq %rcx, 8(%rdi)63; SSE2-NEXT: movq %rcx, (%rdi)64; SSE2-NEXT: retq65;66; SSE4-LABEL: memset_16:67; SSE4: # %bb.0:68; SSE4-NEXT: movd %esi, %xmm069; SSE4-NEXT: pxor %xmm1, %xmm170; SSE4-NEXT: pshufb %xmm1, %xmm071; SSE4-NEXT: movdqu %xmm0, (%rdi)72; SSE4-NEXT: retq73;74; AVX-LABEL: memset_16:75; AVX: # %bb.0:76; AVX-NEXT: vmovd %esi, %xmm077; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm178; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm079; AVX-NEXT: vmovdqu %xmm0, (%rdi)80; AVX-NEXT: retq81;82; AVX512-LABEL: memset_16:83; AVX512: # %bb.0:84; AVX512-NEXT: vmovd %esi, %xmm085; AVX512-NEXT: vpbroadcastb %xmm0, %xmm086; AVX512-NEXT: vmovdqu %xmm0, (%rdi)87; AVX512-NEXT: retq88 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 16, i1 0)89 ret void90}91 92define void @memset_32(ptr %a, i8 %value) nounwind {93; SSE2-LABEL: memset_32:94; SSE2: # %bb.0:95; SSE2-NEXT: movzbl %sil, %eax96; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x10101010101010197; SSE2-NEXT: imulq %rax, %rcx98; SSE2-NEXT: movq %rcx, 24(%rdi)99; SSE2-NEXT: movq %rcx, 16(%rdi)100; SSE2-NEXT: movq %rcx, 8(%rdi)101; SSE2-NEXT: movq %rcx, (%rdi)102; SSE2-NEXT: retq103;104; SSE4-LABEL: memset_32:105; SSE4: # %bb.0:106; SSE4-NEXT: movd %esi, %xmm0107; SSE4-NEXT: pxor %xmm1, %xmm1108; SSE4-NEXT: pshufb %xmm1, %xmm0109; SSE4-NEXT: movdqu %xmm0, 16(%rdi)110; SSE4-NEXT: movdqu %xmm0, (%rdi)111; SSE4-NEXT: retq112;113; AVX-LABEL: memset_32:114; AVX: # %bb.0:115; AVX-NEXT: vmovd %esi, %xmm0116; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1117; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0118; AVX-NEXT: vmovdqu %xmm0, 16(%rdi)119; AVX-NEXT: vmovdqu %xmm0, (%rdi)120; AVX-NEXT: retq121;122; AVX512-LABEL: memset_32:123; AVX512: # %bb.0:124; AVX512-NEXT: vmovd %esi, %xmm0125; AVX512-NEXT: vpbroadcastb %xmm0, %ymm0126; AVX512-NEXT: vmovdqu %ymm0, (%rdi)127; AVX512-NEXT: vzeroupper128; AVX512-NEXT: retq129 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 32, i1 0)130 ret void131}132 133define void @memset_64(ptr %a, i8 %value) nounwind {134; SSE2-LABEL: memset_64:135; SSE2: # %bb.0:136; SSE2-NEXT: movzbl %sil, %eax137; SSE2-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101138; SSE2-NEXT: imulq %rax, %rcx139; SSE2-NEXT: movq %rcx, 56(%rdi)140; SSE2-NEXT: movq %rcx, 48(%rdi)141; SSE2-NEXT: movq %rcx, 40(%rdi)142; SSE2-NEXT: movq %rcx, 32(%rdi)143; SSE2-NEXT: movq %rcx, 24(%rdi)144; SSE2-NEXT: movq %rcx, 16(%rdi)145; SSE2-NEXT: movq %rcx, 8(%rdi)146; SSE2-NEXT: movq %rcx, (%rdi)147; SSE2-NEXT: retq148;149; SSE4-LABEL: memset_64:150; SSE4: # %bb.0:151; SSE4-NEXT: movd %esi, %xmm0152; SSE4-NEXT: pxor %xmm1, %xmm1153; SSE4-NEXT: pshufb %xmm1, %xmm0154; SSE4-NEXT: movdqu %xmm0, 48(%rdi)155; SSE4-NEXT: movdqu %xmm0, 32(%rdi)156; SSE4-NEXT: movdqu %xmm0, 16(%rdi)157; SSE4-NEXT: movdqu %xmm0, (%rdi)158; SSE4-NEXT: retq159;160; AVX-LABEL: memset_64:161; AVX: # %bb.0:162; AVX-NEXT: vmovd %esi, %xmm0163; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1164; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0165; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0166; AVX-NEXT: vmovups %ymm0, 32(%rdi)167; AVX-NEXT: vmovups %ymm0, (%rdi)168; AVX-NEXT: vzeroupper169; AVX-NEXT: retq170;171; AVX512-LABEL: memset_64:172; AVX512: # %bb.0:173; AVX512-NEXT: movzbl %sil, %eax174; AVX512-NEXT: imull $16843009, %eax, %eax # imm = 0x1010101175; AVX512-NEXT: vpbroadcastd %eax, %zmm0176; AVX512-NEXT: vmovdqu64 %zmm0, (%rdi)177; AVX512-NEXT: vzeroupper178; AVX512-NEXT: retq179 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 64, i1 0)180 ret void181}182 183; /////////////////////////////////////////////////////////////////////////////184 185define void @aligned_memset_16(ptr align 16 %a, i8 %value) nounwind {186; SSE2-LABEL: aligned_memset_16:187; SSE2: # %bb.0:188; SSE2-NEXT: movd %esi, %xmm0189; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]190; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]191; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]192; SSE2-NEXT: movdqa %xmm0, (%rdi)193; SSE2-NEXT: retq194;195; SSE4-LABEL: aligned_memset_16:196; SSE4: # %bb.0:197; SSE4-NEXT: movd %esi, %xmm0198; SSE4-NEXT: pxor %xmm1, %xmm1199; SSE4-NEXT: pshufb %xmm1, %xmm0200; SSE4-NEXT: movdqa %xmm0, (%rdi)201; SSE4-NEXT: retq202;203; AVX-LABEL: aligned_memset_16:204; AVX: # %bb.0:205; AVX-NEXT: vmovd %esi, %xmm0206; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1207; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0208; AVX-NEXT: vmovdqa %xmm0, (%rdi)209; AVX-NEXT: retq210;211; AVX512-LABEL: aligned_memset_16:212; AVX512: # %bb.0:213; AVX512-NEXT: vmovd %esi, %xmm0214; AVX512-NEXT: vpbroadcastb %xmm0, %xmm0215; AVX512-NEXT: vmovdqa %xmm0, (%rdi)216; AVX512-NEXT: retq217 tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 %value, i64 16, i1 0)218 ret void219}220 221define void @aligned_memset_32(ptr align 32 %a, i8 %value) nounwind {222; SSE2-LABEL: aligned_memset_32:223; SSE2: # %bb.0:224; SSE2-NEXT: movd %esi, %xmm0225; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]226; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]227; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]228; SSE2-NEXT: movdqa %xmm0, 16(%rdi)229; SSE2-NEXT: movdqa %xmm0, (%rdi)230; SSE2-NEXT: retq231;232; SSE4-LABEL: aligned_memset_32:233; SSE4: # %bb.0:234; SSE4-NEXT: movd %esi, %xmm0235; SSE4-NEXT: pxor %xmm1, %xmm1236; SSE4-NEXT: pshufb %xmm1, %xmm0237; SSE4-NEXT: movdqa %xmm0, 16(%rdi)238; SSE4-NEXT: movdqa %xmm0, (%rdi)239; SSE4-NEXT: retq240;241; AVX-LABEL: aligned_memset_32:242; AVX: # %bb.0:243; AVX-NEXT: vmovd %esi, %xmm0244; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1245; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0246; AVX-NEXT: vmovdqa %xmm0, 16(%rdi)247; AVX-NEXT: vmovdqa %xmm0, (%rdi)248; AVX-NEXT: retq249;250; AVX512-LABEL: aligned_memset_32:251; AVX512: # %bb.0:252; AVX512-NEXT: vmovd %esi, %xmm0253; AVX512-NEXT: vpbroadcastb %xmm0, %ymm0254; AVX512-NEXT: vmovdqa %ymm0, (%rdi)255; AVX512-NEXT: vzeroupper256; AVX512-NEXT: retq257 tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 %value, i64 32, i1 0)258 ret void259}260 261define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind {262; SSE2-LABEL: aligned_memset_64:263; SSE2: # %bb.0:264; SSE2-NEXT: movd %esi, %xmm0265; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]266; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]267; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]268; SSE2-NEXT: movdqa %xmm0, 48(%rdi)269; SSE2-NEXT: movdqa %xmm0, 32(%rdi)270; SSE2-NEXT: movdqa %xmm0, 16(%rdi)271; SSE2-NEXT: movdqa %xmm0, (%rdi)272; SSE2-NEXT: retq273;274; SSE4-LABEL: aligned_memset_64:275; SSE4: # %bb.0:276; SSE4-NEXT: movd %esi, %xmm0277; SSE4-NEXT: pxor %xmm1, %xmm1278; SSE4-NEXT: pshufb %xmm1, %xmm0279; SSE4-NEXT: movdqa %xmm0, 48(%rdi)280; SSE4-NEXT: movdqa %xmm0, 32(%rdi)281; SSE4-NEXT: movdqa %xmm0, 16(%rdi)282; SSE4-NEXT: movdqa %xmm0, (%rdi)283; SSE4-NEXT: retq284;285; AVX-LABEL: aligned_memset_64:286; AVX: # %bb.0:287; AVX-NEXT: vmovd %esi, %xmm0288; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1289; AVX-NEXT: vpshufb %xmm1, %xmm0, %xmm0290; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0291; AVX-NEXT: vmovaps %ymm0, 32(%rdi)292; AVX-NEXT: vmovaps %ymm0, (%rdi)293; AVX-NEXT: vzeroupper294; AVX-NEXT: retq295;296; AVX512-LABEL: aligned_memset_64:297; AVX512: # %bb.0:298; AVX512-NEXT: movzbl %sil, %eax299; AVX512-NEXT: imull $16843009, %eax, %eax # imm = 0x1010101300; AVX512-NEXT: vpbroadcastd %eax, %zmm0301; AVX512-NEXT: vmovdqa64 %zmm0, (%rdi)302; AVX512-NEXT: vzeroupper303; AVX512-NEXT: retq304 tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 %value, i64 64, i1 0)305 ret void306}307 308; /////////////////////////////////////////////////////////////////////////////309 310define void @bzero_1(ptr %a) nounwind {311; GPR-LABEL: bzero_1:312; GPR: # %bb.0:313; GPR-NEXT: movb $0, (%rdi)314; GPR-NEXT: retq315 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 1, i1 0)316 ret void317}318 319define void @bzero_2(ptr %a) nounwind {320; GPR-LABEL: bzero_2:321; GPR: # %bb.0:322; GPR-NEXT: movw $0, (%rdi)323; GPR-NEXT: retq324 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 2, i1 0)325 ret void326}327 328define void @bzero_4(ptr %a) nounwind {329; GPR-LABEL: bzero_4:330; GPR: # %bb.0:331; GPR-NEXT: movl $0, (%rdi)332; GPR-NEXT: retq333 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 4, i1 0)334 ret void335}336 337define void @bzero_8(ptr %a) nounwind {338; GPR-LABEL: bzero_8:339; GPR: # %bb.0:340; GPR-NEXT: movq $0, (%rdi)341; GPR-NEXT: retq342 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 8, i1 0)343 ret void344}345 346define void @bzero_16(ptr %a) nounwind {347; SSE2-LABEL: bzero_16:348; SSE2: # %bb.0:349; SSE2-NEXT: movq $0, 8(%rdi)350; SSE2-NEXT: movq $0, (%rdi)351; SSE2-NEXT: retq352;353; SSE4-LABEL: bzero_16:354; SSE4: # %bb.0:355; SSE4-NEXT: xorps %xmm0, %xmm0356; SSE4-NEXT: movups %xmm0, (%rdi)357; SSE4-NEXT: retq358;359; AVX-LABEL: bzero_16:360; AVX: # %bb.0:361; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0362; AVX-NEXT: vmovups %xmm0, (%rdi)363; AVX-NEXT: retq364;365; AVX512-LABEL: bzero_16:366; AVX512: # %bb.0:367; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0368; AVX512-NEXT: vmovups %xmm0, (%rdi)369; AVX512-NEXT: retq370 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 16, i1 0)371 ret void372}373 374define void @bzero_32(ptr %a) nounwind {375; SSE2-LABEL: bzero_32:376; SSE2: # %bb.0:377; SSE2-NEXT: movq $0, 24(%rdi)378; SSE2-NEXT: movq $0, 16(%rdi)379; SSE2-NEXT: movq $0, 8(%rdi)380; SSE2-NEXT: movq $0, (%rdi)381; SSE2-NEXT: retq382;383; SSE4-LABEL: bzero_32:384; SSE4: # %bb.0:385; SSE4-NEXT: xorps %xmm0, %xmm0386; SSE4-NEXT: movups %xmm0, 16(%rdi)387; SSE4-NEXT: movups %xmm0, (%rdi)388; SSE4-NEXT: retq389;390; AVX-LABEL: bzero_32:391; AVX: # %bb.0:392; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0393; AVX-NEXT: vmovups %ymm0, (%rdi)394; AVX-NEXT: vzeroupper395; AVX-NEXT: retq396;397; AVX512-LABEL: bzero_32:398; AVX512: # %bb.0:399; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0400; AVX512-NEXT: vmovups %ymm0, (%rdi)401; AVX512-NEXT: vzeroupper402; AVX512-NEXT: retq403 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 32, i1 0)404 ret void405}406 407define void @bzero_64(ptr %a) nounwind {408; SSE2-LABEL: bzero_64:409; SSE2: # %bb.0:410; SSE2-NEXT: movq $0, 56(%rdi)411; SSE2-NEXT: movq $0, 48(%rdi)412; SSE2-NEXT: movq $0, 40(%rdi)413; SSE2-NEXT: movq $0, 32(%rdi)414; SSE2-NEXT: movq $0, 24(%rdi)415; SSE2-NEXT: movq $0, 16(%rdi)416; SSE2-NEXT: movq $0, 8(%rdi)417; SSE2-NEXT: movq $0, (%rdi)418; SSE2-NEXT: retq419;420; SSE4-LABEL: bzero_64:421; SSE4: # %bb.0:422; SSE4-NEXT: xorps %xmm0, %xmm0423; SSE4-NEXT: movups %xmm0, 48(%rdi)424; SSE4-NEXT: movups %xmm0, 32(%rdi)425; SSE4-NEXT: movups %xmm0, 16(%rdi)426; SSE4-NEXT: movups %xmm0, (%rdi)427; SSE4-NEXT: retq428;429; AVX-LABEL: bzero_64:430; AVX: # %bb.0:431; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0432; AVX-NEXT: vmovups %ymm0, 32(%rdi)433; AVX-NEXT: vmovups %ymm0, (%rdi)434; AVX-NEXT: vzeroupper435; AVX-NEXT: retq436;437; AVX512-LABEL: bzero_64:438; AVX512: # %bb.0:439; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0440; AVX512-NEXT: vmovups %zmm0, (%rdi)441; AVX512-NEXT: vzeroupper442; AVX512-NEXT: retq443 tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 64, i1 0)444 ret void445}446 447; /////////////////////////////////////////////////////////////////////////////448 449define void @aligned_bzero_16(ptr %a) nounwind {450; SSE2-LABEL: aligned_bzero_16:451; SSE2: # %bb.0:452; SSE2-NEXT: xorps %xmm0, %xmm0453; SSE2-NEXT: movaps %xmm0, (%rdi)454; SSE2-NEXT: retq455;456; SSE4-LABEL: aligned_bzero_16:457; SSE4: # %bb.0:458; SSE4-NEXT: xorps %xmm0, %xmm0459; SSE4-NEXT: movaps %xmm0, (%rdi)460; SSE4-NEXT: retq461;462; AVX-LABEL: aligned_bzero_16:463; AVX: # %bb.0:464; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0465; AVX-NEXT: vmovaps %xmm0, (%rdi)466; AVX-NEXT: retq467;468; AVX512-LABEL: aligned_bzero_16:469; AVX512: # %bb.0:470; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0471; AVX512-NEXT: vmovaps %xmm0, (%rdi)472; AVX512-NEXT: retq473 tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 0, i64 16, i1 0)474 ret void475}476 477define void @aligned_bzero_32(ptr %a) nounwind {478; SSE2-LABEL: aligned_bzero_32:479; SSE2: # %bb.0:480; SSE2-NEXT: xorps %xmm0, %xmm0481; SSE2-NEXT: movaps %xmm0, 16(%rdi)482; SSE2-NEXT: movaps %xmm0, (%rdi)483; SSE2-NEXT: retq484;485; SSE4-LABEL: aligned_bzero_32:486; SSE4: # %bb.0:487; SSE4-NEXT: xorps %xmm0, %xmm0488; SSE4-NEXT: movaps %xmm0, 16(%rdi)489; SSE4-NEXT: movaps %xmm0, (%rdi)490; SSE4-NEXT: retq491;492; AVX-LABEL: aligned_bzero_32:493; AVX: # %bb.0:494; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0495; AVX-NEXT: vmovaps %ymm0, (%rdi)496; AVX-NEXT: vzeroupper497; AVX-NEXT: retq498;499; AVX512-LABEL: aligned_bzero_32:500; AVX512: # %bb.0:501; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0502; AVX512-NEXT: vmovaps %ymm0, (%rdi)503; AVX512-NEXT: vzeroupper504; AVX512-NEXT: retq505 tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 0, i64 32, i1 0)506 ret void507}508 509define void @aligned_bzero_64(ptr %a) nounwind {510; SSE2-LABEL: aligned_bzero_64:511; SSE2: # %bb.0:512; SSE2-NEXT: xorps %xmm0, %xmm0513; SSE2-NEXT: movaps %xmm0, 48(%rdi)514; SSE2-NEXT: movaps %xmm0, 32(%rdi)515; SSE2-NEXT: movaps %xmm0, 16(%rdi)516; SSE2-NEXT: movaps %xmm0, (%rdi)517; SSE2-NEXT: retq518;519; SSE4-LABEL: aligned_bzero_64:520; SSE4: # %bb.0:521; SSE4-NEXT: xorps %xmm0, %xmm0522; SSE4-NEXT: movaps %xmm0, 48(%rdi)523; SSE4-NEXT: movaps %xmm0, 32(%rdi)524; SSE4-NEXT: movaps %xmm0, 16(%rdi)525; SSE4-NEXT: movaps %xmm0, (%rdi)526; SSE4-NEXT: retq527;528; AVX-LABEL: aligned_bzero_64:529; AVX: # %bb.0:530; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0531; AVX-NEXT: vmovaps %ymm0, 32(%rdi)532; AVX-NEXT: vmovaps %ymm0, (%rdi)533; AVX-NEXT: vzeroupper534; AVX-NEXT: retq535;536; AVX512-LABEL: aligned_bzero_64:537; AVX512: # %bb.0:538; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0539; AVX512-NEXT: vmovaps %zmm0, (%rdi)540; AVX512-NEXT: vzeroupper541; AVX512-NEXT: retq542 tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 64, i1 0)543 ret void544}545