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1; REQUIRES: asserts2; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s3; RUN: llc -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s -o /dev/null 2>&1 | FileCheck -check-prefix=DBGDAG %s4 5; It's OK to merge the load / store of the first 2 components, but6; they must not be placed on the same chain after merging.7 8; X86-LABEL: {{^}}merge_store_partial_overlap_load:9; X86-DAG: movzwl ([[BASEREG:%[a-z]+]]), %e[[LO2:[a-z]+]]10; X86-DAG: movzbl 2([[BASEREG]]), %e[[HI1:[a-z]]]11 12; X86-NEXT: movw %[[LO2]], 1([[BASEREG]])13; X86-NEXT: movb %[[HI1]]l, 3([[BASEREG]])14; X86-NEXT: retq15 16; DBGDAG-LABEL: Optimized legalized selection DAG: %bb.0 'merge_store_partial_overlap_load:'17; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch,glue = EntryToken18; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],19; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add {{(nuw )?}}[[BASEPTR]], Constant:i64<2>20 21; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<(load (s16) from %ir.tmp81, align 1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i6422; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<(load (s8) from %ir.tmp12)> [[ENTRYTOKEN]], [[ADDPTR]], undef:i6423 24; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<(store (s8) into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], t{{[0-9]+}}, undef:i6425; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:126; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<(store (s16) into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i6427 28; DBGDAG: X86ISD::RET_GLUE t{{[0-9]+}},29 30; DBGDAG-LABEL: Instruction selection begins31define void @merge_store_partial_overlap_load(ptr %tmp) {32 %tmp8 = getelementptr inbounds [4 x i8], ptr %tmp, i32 0, i8 033 %tmp10 = getelementptr inbounds [4 x i8], ptr %tmp, i32 0, i8 134 %tmp12 = getelementptr inbounds [4 x i8], ptr %tmp, i32 0, i8 235 %tmp14 = getelementptr [4 x i8], ptr %tmp, i32 0, i8 336 37 %tmp9 = load i8, ptr %tmp8, align 1 ; base + 038 %tmp11 = load i8, ptr %tmp10, align 1 ; base + 139 %tmp13 = load i8, ptr %tmp12, align 1 ; base + 240 41 store i8 %tmp9, ptr %tmp10, align 1 ; base + 142 store i8 %tmp11, ptr %tmp12, align 1 ; base + 243 store i8 %tmp13, ptr %tmp14, align 1 ; base + 344 45; Should emit46; load base + 0, base + 147; store base + 1, base + 248; load base + 249; store base + 350 51 ret void52}53