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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=ALL,AVX512F3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512VL-FALLBACK4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW6 7; These test cases are inspired by C++2a std::midpoint().8; See https://bugs.llvm.org/show_bug.cgi?id=409659 10; Using 512-bit vector regs.11 12; ---------------------------------------------------------------------------- ;13; 32-bit width. 512 / 32 = 16 elts.14; ---------------------------------------------------------------------------- ;15 16; Values come from regs17 18define <16 x i32> @vec512_i32_signed_reg_reg(<16 x i32> %a1, <16 x i32> %a2) nounwind {19; ALL-LABEL: vec512_i32_signed_reg_reg:20; ALL: # %bb.0:21; ALL-NEXT: vpminsd %zmm1, %zmm0, %zmm222; ALL-NEXT: vpmaxsd %zmm1, %zmm0, %zmm123; ALL-NEXT: vpsubd %zmm2, %zmm1, %zmm124; ALL-NEXT: vpsrld $1, %zmm1, %zmm125; ALL-NEXT: vpmulld %zmm1, %zmm1, %zmm126; ALL-NEXT: vpaddd %zmm0, %zmm1, %zmm027; ALL-NEXT: retq28 %t3 = icmp sgt <16 x i32> %a1, %a2 ; signed29 %t4 = select <16 x i1> %t3, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>30 %t5 = select <16 x i1> %t3, <16 x i32> %a2, <16 x i32> %a131 %t6 = select <16 x i1> %t3, <16 x i32> %a1, <16 x i32> %a232 %t7 = sub <16 x i32> %t6, %t533 %t16 = lshr <16 x i32> %t7, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>34 %t9 = mul nsw <16 x i32> %t16, %t16 ; signed35 %a10 = add nsw <16 x i32> %t9, %a1 ; signed36 ret <16 x i32> %a1037}38 39define <16 x i32> @vec512_i32_unsigned_reg_reg(<16 x i32> %a1, <16 x i32> %a2) nounwind {40; ALL-LABEL: vec512_i32_unsigned_reg_reg:41; ALL: # %bb.0:42; ALL-NEXT: vpminud %zmm1, %zmm0, %zmm243; ALL-NEXT: vpmaxud %zmm1, %zmm0, %zmm144; ALL-NEXT: vpsubd %zmm2, %zmm1, %zmm145; ALL-NEXT: vpsrld $1, %zmm1, %zmm146; ALL-NEXT: vpmulld %zmm1, %zmm1, %zmm147; ALL-NEXT: vpaddd %zmm0, %zmm1, %zmm048; ALL-NEXT: retq49 %t3 = icmp ugt <16 x i32> %a1, %a250 %t4 = select <16 x i1> %t3, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>51 %t5 = select <16 x i1> %t3, <16 x i32> %a2, <16 x i32> %a152 %t6 = select <16 x i1> %t3, <16 x i32> %a1, <16 x i32> %a253 %t7 = sub <16 x i32> %t6, %t554 %t16 = lshr <16 x i32> %t7, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>55 %t9 = mul <16 x i32> %t16, %t1656 %a10 = add <16 x i32> %t9, %a157 ret <16 x i32> %a1058}59 60; Values are loaded. Only check signed case.61 62define <16 x i32> @vec512_i32_signed_mem_reg(ptr %a1_addr, <16 x i32> %a2) nounwind {63; ALL-LABEL: vec512_i32_signed_mem_reg:64; ALL: # %bb.0:65; ALL-NEXT: vmovdqa64 (%rdi), %zmm166; ALL-NEXT: vpminsd %zmm0, %zmm1, %zmm267; ALL-NEXT: vpmaxsd %zmm0, %zmm1, %zmm068; ALL-NEXT: vpsubd %zmm2, %zmm0, %zmm069; ALL-NEXT: vpsrld $1, %zmm0, %zmm070; ALL-NEXT: vpmulld %zmm0, %zmm0, %zmm071; ALL-NEXT: vpaddd %zmm1, %zmm0, %zmm072; ALL-NEXT: retq73 %a1 = load <16 x i32>, ptr %a1_addr74 %t3 = icmp sgt <16 x i32> %a1, %a2 ; signed75 %t4 = select <16 x i1> %t3, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>76 %t5 = select <16 x i1> %t3, <16 x i32> %a2, <16 x i32> %a177 %t6 = select <16 x i1> %t3, <16 x i32> %a1, <16 x i32> %a278 %t7 = sub <16 x i32> %t6, %t579 %t16 = lshr <16 x i32> %t7, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>80 %t9 = mul nsw <16 x i32> %t16, %t16 ; signed81 %a10 = add nsw <16 x i32> %t9, %a1 ; signed82 ret <16 x i32> %a1083}84 85define <16 x i32> @vec512_i32_signed_reg_mem(<16 x i32> %a1, ptr %a2_addr) nounwind {86; ALL-LABEL: vec512_i32_signed_reg_mem:87; ALL: # %bb.0:88; ALL-NEXT: vmovdqa64 (%rdi), %zmm189; ALL-NEXT: vpminsd %zmm1, %zmm0, %zmm290; ALL-NEXT: vpmaxsd %zmm1, %zmm0, %zmm191; ALL-NEXT: vpsubd %zmm2, %zmm1, %zmm192; ALL-NEXT: vpsrld $1, %zmm1, %zmm193; ALL-NEXT: vpmulld %zmm1, %zmm1, %zmm194; ALL-NEXT: vpaddd %zmm0, %zmm1, %zmm095; ALL-NEXT: retq96 %a2 = load <16 x i32>, ptr %a2_addr97 %t3 = icmp sgt <16 x i32> %a1, %a2 ; signed98 %t4 = select <16 x i1> %t3, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>99 %t5 = select <16 x i1> %t3, <16 x i32> %a2, <16 x i32> %a1100 %t6 = select <16 x i1> %t3, <16 x i32> %a1, <16 x i32> %a2101 %t7 = sub <16 x i32> %t6, %t5102 %t16 = lshr <16 x i32> %t7, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>103 %t9 = mul nsw <16 x i32> %t16, %t16 ; signed104 %a10 = add nsw <16 x i32> %t9, %a1 ; signed105 ret <16 x i32> %a10106}107 108define <16 x i32> @vec512_i32_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {109; ALL-LABEL: vec512_i32_signed_mem_mem:110; ALL: # %bb.0:111; ALL-NEXT: vmovdqa64 (%rdi), %zmm0112; ALL-NEXT: vmovdqa64 (%rsi), %zmm1113; ALL-NEXT: vpminsd %zmm1, %zmm0, %zmm2114; ALL-NEXT: vpmaxsd %zmm1, %zmm0, %zmm1115; ALL-NEXT: vpsubd %zmm2, %zmm1, %zmm1116; ALL-NEXT: vpsrld $1, %zmm1, %zmm1117; ALL-NEXT: vpmulld %zmm1, %zmm1, %zmm1118; ALL-NEXT: vpaddd %zmm0, %zmm1, %zmm0119; ALL-NEXT: retq120 %a1 = load <16 x i32>, ptr %a1_addr121 %a2 = load <16 x i32>, ptr %a2_addr122 %t3 = icmp sgt <16 x i32> %a1, %a2 ; signed123 %t4 = select <16 x i1> %t3, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>124 %t5 = select <16 x i1> %t3, <16 x i32> %a2, <16 x i32> %a1125 %t6 = select <16 x i1> %t3, <16 x i32> %a1, <16 x i32> %a2126 %t7 = sub <16 x i32> %t6, %t5127 %t16 = lshr <16 x i32> %t7, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>128 %t9 = mul nsw <16 x i32> %t16, %t16 ; signed129 %a10 = add nsw <16 x i32> %t9, %a1 ; signed130 ret <16 x i32> %a10131}132 133; ---------------------------------------------------------------------------- ;134; 64-bit width. 512 / 64 = 8 elts.135; ---------------------------------------------------------------------------- ;136 137; Values come from regs138 139define <8 x i64> @vec512_i64_signed_reg_reg(<8 x i64> %a1, <8 x i64> %a2) nounwind {140; ALL-LABEL: vec512_i64_signed_reg_reg:141; ALL: # %bb.0:142; ALL-NEXT: vpcmpgtq %zmm1, %zmm0, %k1143; ALL-NEXT: vpminsq %zmm1, %zmm0, %zmm2144; ALL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm1145; ALL-NEXT: vpsubq %zmm2, %zmm1, %zmm1146; ALL-NEXT: vpsrlq $1, %zmm1, %zmm1147; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2148; ALL-NEXT: vpsubq %zmm1, %zmm2, %zmm1 {%k1}149; ALL-NEXT: vpaddq %zmm0, %zmm1, %zmm0150; ALL-NEXT: retq151 %t3 = icmp sgt <8 x i64> %a1, %a2 ; signed152 %t4 = select <8 x i1> %t3, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>153 %t5 = select <8 x i1> %t3, <8 x i64> %a2, <8 x i64> %a1154 %t6 = select <8 x i1> %t3, <8 x i64> %a1, <8 x i64> %a2155 %t7 = sub <8 x i64> %t6, %t5156 %t8 = lshr <8 x i64> %t7, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>157 %t9 = mul nsw <8 x i64> %t8, %t4 ; signed158 %a10 = add nsw <8 x i64> %t9, %a1 ; signed159 ret <8 x i64> %a10160}161 162define <8 x i64> @vec512_i64_unsigned_reg_reg(<8 x i64> %a1, <8 x i64> %a2) nounwind {163; ALL-LABEL: vec512_i64_unsigned_reg_reg:164; ALL: # %bb.0:165; ALL-NEXT: vpcmpnleuq %zmm1, %zmm0, %k1166; ALL-NEXT: vpminuq %zmm1, %zmm0, %zmm2167; ALL-NEXT: vpmaxuq %zmm1, %zmm0, %zmm1168; ALL-NEXT: vpsubq %zmm2, %zmm1, %zmm1169; ALL-NEXT: vpsrlq $1, %zmm1, %zmm1170; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2171; ALL-NEXT: vpsubq %zmm1, %zmm2, %zmm1 {%k1}172; ALL-NEXT: vpaddq %zmm0, %zmm1, %zmm0173; ALL-NEXT: retq174 %t3 = icmp ugt <8 x i64> %a1, %a2175 %t4 = select <8 x i1> %t3, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>176 %t5 = select <8 x i1> %t3, <8 x i64> %a2, <8 x i64> %a1177 %t6 = select <8 x i1> %t3, <8 x i64> %a1, <8 x i64> %a2178 %t7 = sub <8 x i64> %t6, %t5179 %t8 = lshr <8 x i64> %t7, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>180 %t9 = mul <8 x i64> %t8, %t4181 %a10 = add <8 x i64> %t9, %a1182 ret <8 x i64> %a10183}184 185; Values are loaded. Only check signed case.186 187define <8 x i64> @vec512_i64_signed_mem_reg(ptr %a1_addr, <8 x i64> %a2) nounwind {188; ALL-LABEL: vec512_i64_signed_mem_reg:189; ALL: # %bb.0:190; ALL-NEXT: vmovdqa64 (%rdi), %zmm1191; ALL-NEXT: vpcmpgtq %zmm0, %zmm1, %k1192; ALL-NEXT: vpminsq %zmm0, %zmm1, %zmm2193; ALL-NEXT: vpmaxsq %zmm0, %zmm1, %zmm0194; ALL-NEXT: vpsubq %zmm2, %zmm0, %zmm0195; ALL-NEXT: vpsrlq $1, %zmm0, %zmm0196; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2197; ALL-NEXT: vpsubq %zmm0, %zmm2, %zmm0 {%k1}198; ALL-NEXT: vpaddq %zmm1, %zmm0, %zmm0199; ALL-NEXT: retq200 %a1 = load <8 x i64>, ptr %a1_addr201 %t3 = icmp sgt <8 x i64> %a1, %a2 ; signed202 %t4 = select <8 x i1> %t3, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>203 %t5 = select <8 x i1> %t3, <8 x i64> %a2, <8 x i64> %a1204 %t6 = select <8 x i1> %t3, <8 x i64> %a1, <8 x i64> %a2205 %t7 = sub <8 x i64> %t6, %t5206 %t8 = lshr <8 x i64> %t7, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>207 %t9 = mul nsw <8 x i64> %t8, %t4 ; signed208 %a10 = add nsw <8 x i64> %t9, %a1 ; signed209 ret <8 x i64> %a10210}211 212define <8 x i64> @vec512_i64_signed_reg_mem(<8 x i64> %a1, ptr %a2_addr) nounwind {213; ALL-LABEL: vec512_i64_signed_reg_mem:214; ALL: # %bb.0:215; ALL-NEXT: vmovdqa64 (%rdi), %zmm1216; ALL-NEXT: vpcmpgtq %zmm1, %zmm0, %k1217; ALL-NEXT: vpminsq %zmm1, %zmm0, %zmm2218; ALL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm1219; ALL-NEXT: vpsubq %zmm2, %zmm1, %zmm1220; ALL-NEXT: vpsrlq $1, %zmm1, %zmm1221; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2222; ALL-NEXT: vpsubq %zmm1, %zmm2, %zmm1 {%k1}223; ALL-NEXT: vpaddq %zmm0, %zmm1, %zmm0224; ALL-NEXT: retq225 %a2 = load <8 x i64>, ptr %a2_addr226 %t3 = icmp sgt <8 x i64> %a1, %a2 ; signed227 %t4 = select <8 x i1> %t3, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>228 %t5 = select <8 x i1> %t3, <8 x i64> %a2, <8 x i64> %a1229 %t6 = select <8 x i1> %t3, <8 x i64> %a1, <8 x i64> %a2230 %t7 = sub <8 x i64> %t6, %t5231 %t8 = lshr <8 x i64> %t7, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>232 %t9 = mul nsw <8 x i64> %t8, %t4 ; signed233 %a10 = add nsw <8 x i64> %t9, %a1 ; signed234 ret <8 x i64> %a10235}236 237define <8 x i64> @vec512_i64_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {238; ALL-LABEL: vec512_i64_signed_mem_mem:239; ALL: # %bb.0:240; ALL-NEXT: vmovdqa64 (%rdi), %zmm0241; ALL-NEXT: vmovdqa64 (%rsi), %zmm1242; ALL-NEXT: vpcmpgtq %zmm1, %zmm0, %k1243; ALL-NEXT: vpminsq %zmm1, %zmm0, %zmm2244; ALL-NEXT: vpmaxsq %zmm1, %zmm0, %zmm1245; ALL-NEXT: vpsubq %zmm2, %zmm1, %zmm1246; ALL-NEXT: vpsrlq $1, %zmm1, %zmm1247; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2248; ALL-NEXT: vpsubq %zmm1, %zmm2, %zmm1 {%k1}249; ALL-NEXT: vpaddq %zmm0, %zmm1, %zmm0250; ALL-NEXT: retq251 %a1 = load <8 x i64>, ptr %a1_addr252 %a2 = load <8 x i64>, ptr %a2_addr253 %t3 = icmp sgt <8 x i64> %a1, %a2 ; signed254 %t4 = select <8 x i1> %t3, <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>255 %t5 = select <8 x i1> %t3, <8 x i64> %a2, <8 x i64> %a1256 %t6 = select <8 x i1> %t3, <8 x i64> %a1, <8 x i64> %a2257 %t7 = sub <8 x i64> %t6, %t5258 %t8 = lshr <8 x i64> %t7, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>259 %t9 = mul nsw <8 x i64> %t8, %t4 ; signed260 %a10 = add nsw <8 x i64> %t9, %a1 ; signed261 ret <8 x i64> %a10262}263 264; ---------------------------------------------------------------------------- ;265; 16-bit width. 512 / 16 = 32 elts.266; ---------------------------------------------------------------------------- ;267 268; Values come from regs269 270define <32 x i16> @vec512_i16_signed_reg_reg(<32 x i16> %a1, <32 x i16> %a2) nounwind {271; AVX512F-LABEL: vec512_i16_signed_reg_reg:272; AVX512F: # %bb.0:273; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2274; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3275; AVX512F-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm4276; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm5277; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4278; AVX512F-NEXT: vpminsw %ymm2, %ymm3, %ymm5279; AVX512F-NEXT: vpmaxsw %ymm2, %ymm3, %ymm2280; AVX512F-NEXT: vpsubw %ymm5, %ymm2, %ymm2281; AVX512F-NEXT: vpminsw %ymm1, %ymm0, %ymm5282; AVX512F-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1283; AVX512F-NEXT: vpsubw %ymm5, %ymm1, %ymm1284; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1285; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2286; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5287; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6288; AVX512F-NEXT: vpsubw %ymm2, %ymm6, %ymm2289; AVX512F-NEXT: vpsubw %ymm1, %ymm6, %ymm1290; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1291; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))292; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2293; AVX512F-NEXT: vpaddw %ymm3, %ymm2, %ymm2294; AVX512F-NEXT: vpaddw %ymm0, %ymm1, %ymm0295; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0296; AVX512F-NEXT: retq297;298; AVX512VL-FALLBACK-LABEL: vec512_i16_signed_reg_reg:299; AVX512VL-FALLBACK: # %bb.0:300; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2301; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm3302; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm4303; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm5304; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4305; AVX512VL-FALLBACK-NEXT: vpminsw %ymm2, %ymm3, %ymm5306; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm2, %ymm3, %ymm2307; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm2, %ymm2308; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm0, %ymm5309; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm0, %ymm1310; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm1, %ymm1311; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1312; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2313; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5314; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6315; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm6, %ymm2316; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm6, %ymm1317; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1318; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))319; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2320; AVX512VL-FALLBACK-NEXT: vpaddw %ymm3, %ymm2, %ymm2321; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm1, %ymm0322; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0323; AVX512VL-FALLBACK-NEXT: retq324;325; AVX512BW-LABEL: vec512_i16_signed_reg_reg:326; AVX512BW: # %bb.0:327; AVX512BW-NEXT: vpcmpgtw %zmm1, %zmm0, %k1328; AVX512BW-NEXT: vpminsw %zmm1, %zmm0, %zmm2329; AVX512BW-NEXT: vpmaxsw %zmm1, %zmm0, %zmm1330; AVX512BW-NEXT: vpsubw %zmm2, %zmm1, %zmm1331; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1332; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2333; AVX512BW-NEXT: vpsubw %zmm1, %zmm2, %zmm1 {%k1}334; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0335; AVX512BW-NEXT: retq336 %t3 = icmp sgt <32 x i16> %a1, %a2 ; signed337 %t4 = select <32 x i1> %t3, <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>338 %t5 = select <32 x i1> %t3, <32 x i16> %a2, <32 x i16> %a1339 %t6 = select <32 x i1> %t3, <32 x i16> %a1, <32 x i16> %a2340 %t7 = sub <32 x i16> %t6, %t5341 %t16 = lshr <32 x i16> %t7, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>342 %t9 = mul nsw <32 x i16> %t16, %t4 ; signed343 %a10 = add nsw <32 x i16> %t9, %a1 ; signed344 ret <32 x i16> %a10345}346 347define <32 x i16> @vec512_i16_unsigned_reg_reg(<32 x i16> %a1, <32 x i16> %a2) nounwind {348; AVX512F-LABEL: vec512_i16_unsigned_reg_reg:349; AVX512F: # %bb.0:350; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2351; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3352; AVX512F-NEXT: vpminuw %ymm2, %ymm3, %ymm4353; AVX512F-NEXT: vpcmpeqw %ymm4, %ymm3, %ymm5354; AVX512F-NEXT: vpminuw %ymm1, %ymm0, %ymm6355; AVX512F-NEXT: vpcmpeqw %ymm6, %ymm0, %ymm7356; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5357; AVX512F-NEXT: vpmaxuw %ymm2, %ymm3, %ymm2358; AVX512F-NEXT: vpsubw %ymm4, %ymm2, %ymm2359; AVX512F-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1360; AVX512F-NEXT: vpsubw %ymm6, %ymm1, %ymm1361; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1362; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2363; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4364; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6365; AVX512F-NEXT: vpsubw %ymm2, %ymm6, %ymm2366; AVX512F-NEXT: vpsubw %ymm1, %ymm6, %ymm1367; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1368; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 ^ (zmm5 & (zmm1 ^ zmm4))369; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2370; AVX512F-NEXT: vpaddw %ymm3, %ymm2, %ymm2371; AVX512F-NEXT: vpaddw %ymm0, %ymm1, %ymm0372; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0373; AVX512F-NEXT: retq374;375; AVX512VL-FALLBACK-LABEL: vec512_i16_unsigned_reg_reg:376; AVX512VL-FALLBACK: # %bb.0:377; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2378; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm3379; AVX512VL-FALLBACK-NEXT: vpminuw %ymm2, %ymm3, %ymm4380; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm4, %ymm3, %ymm5381; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm6382; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm6, %ymm0, %ymm7383; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5384; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm2, %ymm3, %ymm2385; AVX512VL-FALLBACK-NEXT: vpsubw %ymm4, %ymm2, %ymm2386; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1387; AVX512VL-FALLBACK-NEXT: vpsubw %ymm6, %ymm1, %ymm1388; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1389; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2390; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4391; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6392; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm6, %ymm2393; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm6, %ymm1394; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1395; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 ^ (zmm5 & (zmm1 ^ zmm4))396; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2397; AVX512VL-FALLBACK-NEXT: vpaddw %ymm3, %ymm2, %ymm2398; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm1, %ymm0399; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0400; AVX512VL-FALLBACK-NEXT: retq401;402; AVX512BW-LABEL: vec512_i16_unsigned_reg_reg:403; AVX512BW: # %bb.0:404; AVX512BW-NEXT: vpcmpnleuw %zmm1, %zmm0, %k1405; AVX512BW-NEXT: vpminuw %zmm1, %zmm0, %zmm2406; AVX512BW-NEXT: vpmaxuw %zmm1, %zmm0, %zmm1407; AVX512BW-NEXT: vpsubw %zmm2, %zmm1, %zmm1408; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1409; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2410; AVX512BW-NEXT: vpsubw %zmm1, %zmm2, %zmm1 {%k1}411; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0412; AVX512BW-NEXT: retq413 %t3 = icmp ugt <32 x i16> %a1, %a2414 %t4 = select <32 x i1> %t3, <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>415 %t5 = select <32 x i1> %t3, <32 x i16> %a2, <32 x i16> %a1416 %t6 = select <32 x i1> %t3, <32 x i16> %a1, <32 x i16> %a2417 %t7 = sub <32 x i16> %t6, %t5418 %t16 = lshr <32 x i16> %t7, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>419 %t9 = mul <32 x i16> %t16, %t4420 %a10 = add <32 x i16> %t9, %a1421 ret <32 x i16> %a10422}423 424; Values are loaded. Only check signed case.425 426define <32 x i16> @vec512_i16_signed_mem_reg(ptr %a1_addr, <32 x i16> %a2) nounwind {427; AVX512F-LABEL: vec512_i16_signed_mem_reg:428; AVX512F: # %bb.0:429; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1430; AVX512F-NEXT: vmovdqa (%rdi), %ymm2431; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm3432; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm3, %ymm4433; AVX512F-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm5434; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4435; AVX512F-NEXT: vpminsw %ymm1, %ymm3, %ymm5436; AVX512F-NEXT: vpmaxsw %ymm1, %ymm3, %ymm1437; AVX512F-NEXT: vpsubw %ymm5, %ymm1, %ymm1438; AVX512F-NEXT: vpminsw %ymm0, %ymm2, %ymm5439; AVX512F-NEXT: vpmaxsw %ymm0, %ymm2, %ymm0440; AVX512F-NEXT: vpsubw %ymm5, %ymm0, %ymm0441; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0442; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1443; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5444; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6445; AVX512F-NEXT: vpsubw %ymm1, %ymm6, %ymm1446; AVX512F-NEXT: vpsubw %ymm0, %ymm6, %ymm0447; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0448; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))449; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1450; AVX512F-NEXT: vpaddw %ymm3, %ymm1, %ymm1451; AVX512F-NEXT: vpaddw %ymm2, %ymm0, %ymm0452; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0453; AVX512F-NEXT: retq454;455; AVX512VL-FALLBACK-LABEL: vec512_i16_signed_mem_reg:456; AVX512VL-FALLBACK: # %bb.0:457; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1458; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm2459; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm3460; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm3, %ymm4461; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm5462; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4463; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm3, %ymm5464; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm3, %ymm1465; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm1, %ymm1466; AVX512VL-FALLBACK-NEXT: vpminsw %ymm0, %ymm2, %ymm5467; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm0, %ymm2, %ymm0468; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm0, %ymm0469; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm0470; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1471; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5472; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6473; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm6, %ymm1474; AVX512VL-FALLBACK-NEXT: vpsubw %ymm0, %ymm6, %ymm0475; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0476; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))477; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1478; AVX512VL-FALLBACK-NEXT: vpaddw %ymm3, %ymm1, %ymm1479; AVX512VL-FALLBACK-NEXT: vpaddw %ymm2, %ymm0, %ymm0480; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0481; AVX512VL-FALLBACK-NEXT: retq482;483; AVX512BW-LABEL: vec512_i16_signed_mem_reg:484; AVX512BW: # %bb.0:485; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm1486; AVX512BW-NEXT: vpcmpgtw %zmm0, %zmm1, %k1487; AVX512BW-NEXT: vpminsw %zmm0, %zmm1, %zmm2488; AVX512BW-NEXT: vpmaxsw %zmm0, %zmm1, %zmm0489; AVX512BW-NEXT: vpsubw %zmm2, %zmm0, %zmm0490; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0491; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2492; AVX512BW-NEXT: vpsubw %zmm0, %zmm2, %zmm0 {%k1}493; AVX512BW-NEXT: vpaddw %zmm1, %zmm0, %zmm0494; AVX512BW-NEXT: retq495 %a1 = load <32 x i16>, ptr %a1_addr496 %t3 = icmp sgt <32 x i16> %a1, %a2 ; signed497 %t4 = select <32 x i1> %t3, <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>498 %t5 = select <32 x i1> %t3, <32 x i16> %a2, <32 x i16> %a1499 %t6 = select <32 x i1> %t3, <32 x i16> %a1, <32 x i16> %a2500 %t7 = sub <32 x i16> %t6, %t5501 %t16 = lshr <32 x i16> %t7, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>502 %t9 = mul nsw <32 x i16> %t16, %t4 ; signed503 %a10 = add nsw <32 x i16> %t9, %a1 ; signed504 ret <32 x i16> %a10505}506 507define <32 x i16> @vec512_i16_signed_reg_mem(<32 x i16> %a1, ptr %a2_addr) nounwind {508; AVX512F-LABEL: vec512_i16_signed_reg_mem:509; AVX512F: # %bb.0:510; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1511; AVX512F-NEXT: vmovdqa (%rdi), %ymm2512; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm3513; AVX512F-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm4514; AVX512F-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm5515; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4516; AVX512F-NEXT: vpminsw %ymm3, %ymm1, %ymm5517; AVX512F-NEXT: vpmaxsw %ymm3, %ymm1, %ymm3518; AVX512F-NEXT: vpsubw %ymm5, %ymm3, %ymm3519; AVX512F-NEXT: vpminsw %ymm2, %ymm0, %ymm5520; AVX512F-NEXT: vpmaxsw %ymm2, %ymm0, %ymm2521; AVX512F-NEXT: vpsubw %ymm5, %ymm2, %ymm2522; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2523; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3524; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm5525; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6526; AVX512F-NEXT: vpsubw %ymm3, %ymm6, %ymm3527; AVX512F-NEXT: vpsubw %ymm2, %ymm6, %ymm2528; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2529; AVX512F-NEXT: vpternlogq {{.*#+}} zmm2 = zmm5 ^ (zmm4 & (zmm2 ^ zmm5))530; AVX512F-NEXT: vextracti64x4 $1, %zmm2, %ymm3531; AVX512F-NEXT: vpaddw %ymm1, %ymm3, %ymm1532; AVX512F-NEXT: vpaddw %ymm0, %ymm2, %ymm0533; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0534; AVX512F-NEXT: retq535;536; AVX512VL-FALLBACK-LABEL: vec512_i16_signed_reg_mem:537; AVX512VL-FALLBACK: # %bb.0:538; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1539; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm2540; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm3541; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm3, %ymm1, %ymm4542; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm2, %ymm0, %ymm5543; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4544; AVX512VL-FALLBACK-NEXT: vpminsw %ymm3, %ymm1, %ymm5545; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm3, %ymm1, %ymm3546; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm3, %ymm3547; AVX512VL-FALLBACK-NEXT: vpminsw %ymm2, %ymm0, %ymm5548; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm2, %ymm0, %ymm2549; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm2, %ymm2550; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2551; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm3, %ymm3552; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm5553; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6554; AVX512VL-FALLBACK-NEXT: vpsubw %ymm3, %ymm6, %ymm3555; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm6, %ymm2556; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2557; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm2 = zmm5 ^ (zmm4 & (zmm2 ^ zmm5))558; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm2, %ymm3559; AVX512VL-FALLBACK-NEXT: vpaddw %ymm1, %ymm3, %ymm1560; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm2, %ymm0561; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0562; AVX512VL-FALLBACK-NEXT: retq563;564; AVX512BW-LABEL: vec512_i16_signed_reg_mem:565; AVX512BW: # %bb.0:566; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm1567; AVX512BW-NEXT: vpcmpgtw %zmm1, %zmm0, %k1568; AVX512BW-NEXT: vpminsw %zmm1, %zmm0, %zmm2569; AVX512BW-NEXT: vpmaxsw %zmm1, %zmm0, %zmm1570; AVX512BW-NEXT: vpsubw %zmm2, %zmm1, %zmm1571; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1572; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2573; AVX512BW-NEXT: vpsubw %zmm1, %zmm2, %zmm1 {%k1}574; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0575; AVX512BW-NEXT: retq576 %a2 = load <32 x i16>, ptr %a2_addr577 %t3 = icmp sgt <32 x i16> %a1, %a2 ; signed578 %t4 = select <32 x i1> %t3, <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>579 %t5 = select <32 x i1> %t3, <32 x i16> %a2, <32 x i16> %a1580 %t6 = select <32 x i1> %t3, <32 x i16> %a1, <32 x i16> %a2581 %t7 = sub <32 x i16> %t6, %t5582 %t16 = lshr <32 x i16> %t7, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>583 %t9 = mul nsw <32 x i16> %t16, %t4 ; signed584 %a10 = add nsw <32 x i16> %t9, %a1 ; signed585 ret <32 x i16> %a10586}587 588define <32 x i16> @vec512_i16_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {589; AVX512F-LABEL: vec512_i16_signed_mem_mem:590; AVX512F: # %bb.0:591; AVX512F-NEXT: vmovdqa (%rsi), %ymm0592; AVX512F-NEXT: vmovdqa 32(%rsi), %ymm1593; AVX512F-NEXT: vmovdqa (%rdi), %ymm2594; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm3595; AVX512F-NEXT: vpcmpgtw %ymm1, %ymm3, %ymm4596; AVX512F-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm5597; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4598; AVX512F-NEXT: vpminsw %ymm1, %ymm3, %ymm5599; AVX512F-NEXT: vpmaxsw %ymm1, %ymm3, %ymm1600; AVX512F-NEXT: vpsubw %ymm5, %ymm1, %ymm1601; AVX512F-NEXT: vpminsw %ymm0, %ymm2, %ymm5602; AVX512F-NEXT: vpmaxsw %ymm0, %ymm2, %ymm0603; AVX512F-NEXT: vpsubw %ymm5, %ymm0, %ymm0604; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0605; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1606; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5607; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6608; AVX512F-NEXT: vpsubw %ymm1, %ymm6, %ymm1609; AVX512F-NEXT: vpsubw %ymm0, %ymm6, %ymm0610; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0611; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))612; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1613; AVX512F-NEXT: vpaddw %ymm3, %ymm1, %ymm1614; AVX512F-NEXT: vpaddw %ymm2, %ymm0, %ymm0615; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0616; AVX512F-NEXT: retq617;618; AVX512VL-FALLBACK-LABEL: vec512_i16_signed_mem_mem:619; AVX512VL-FALLBACK: # %bb.0:620; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %ymm0621; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rsi), %ymm1622; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm2623; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm3624; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm1, %ymm3, %ymm4625; AVX512VL-FALLBACK-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm5626; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4627; AVX512VL-FALLBACK-NEXT: vpminsw %ymm1, %ymm3, %ymm5628; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm1, %ymm3, %ymm1629; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm1, %ymm1630; AVX512VL-FALLBACK-NEXT: vpminsw %ymm0, %ymm2, %ymm5631; AVX512VL-FALLBACK-NEXT: vpmaxsw %ymm0, %ymm2, %ymm0632; AVX512VL-FALLBACK-NEXT: vpsubw %ymm5, %ymm0, %ymm0633; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm0634; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1635; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5636; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6637; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm6, %ymm1638; AVX512VL-FALLBACK-NEXT: vpsubw %ymm0, %ymm6, %ymm0639; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0640; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))641; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1642; AVX512VL-FALLBACK-NEXT: vpaddw %ymm3, %ymm1, %ymm1643; AVX512VL-FALLBACK-NEXT: vpaddw %ymm2, %ymm0, %ymm0644; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0645; AVX512VL-FALLBACK-NEXT: retq646;647; AVX512BW-LABEL: vec512_i16_signed_mem_mem:648; AVX512BW: # %bb.0:649; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm0650; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm1651; AVX512BW-NEXT: vpcmpgtw %zmm1, %zmm0, %k1652; AVX512BW-NEXT: vpminsw %zmm1, %zmm0, %zmm2653; AVX512BW-NEXT: vpmaxsw %zmm1, %zmm0, %zmm1654; AVX512BW-NEXT: vpsubw %zmm2, %zmm1, %zmm1655; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1656; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2657; AVX512BW-NEXT: vpsubw %zmm1, %zmm2, %zmm1 {%k1}658; AVX512BW-NEXT: vpaddw %zmm0, %zmm1, %zmm0659; AVX512BW-NEXT: retq660 %a1 = load <32 x i16>, ptr %a1_addr661 %a2 = load <32 x i16>, ptr %a2_addr662 %t3 = icmp sgt <32 x i16> %a1, %a2 ; signed663 %t4 = select <32 x i1> %t3, <32 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>664 %t5 = select <32 x i1> %t3, <32 x i16> %a2, <32 x i16> %a1665 %t6 = select <32 x i1> %t3, <32 x i16> %a1, <32 x i16> %a2666 %t7 = sub <32 x i16> %t6, %t5667 %t16 = lshr <32 x i16> %t7, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>668 %t9 = mul nsw <32 x i16> %t16, %t4 ; signed669 %a10 = add nsw <32 x i16> %t9, %a1 ; signed670 ret <32 x i16> %a10671}672 673; ---------------------------------------------------------------------------- ;674; 8-bit width. 512 / 8 = 64 elts.675; ---------------------------------------------------------------------------- ;676 677; Values come from regs678 679define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwind {680; AVX512F-LABEL: vec512_i8_signed_reg_reg:681; AVX512F: # %bb.0:682; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2683; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3684; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4685; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5686; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4687; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5688; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1689; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1690; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5691; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2692; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2693; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2694; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]695; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2696; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1697; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1698; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5699; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6700; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2701; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1702; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1703; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))704; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2705; AVX512F-NEXT: vpaddb %ymm3, %ymm2, %ymm2706; AVX512F-NEXT: vpaddb %ymm0, %ymm1, %ymm0707; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0708; AVX512F-NEXT: retq709;710; AVX512VL-FALLBACK-LABEL: vec512_i8_signed_reg_reg:711; AVX512VL-FALLBACK: # %bb.0:712; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2713; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm3714; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4715; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5716; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4717; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm5718; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1719; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1720; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5721; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2722; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2723; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2724; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]725; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm2, %ymm2726; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1727; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm1, %ymm1728; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5729; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6730; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2731; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1732; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1733; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm1 = zmm5 ^ (zmm4 & (zmm1 ^ zmm5))734; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2735; AVX512VL-FALLBACK-NEXT: vpaddb %ymm3, %ymm2, %ymm2736; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm1, %ymm0737; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0738; AVX512VL-FALLBACK-NEXT: retq739;740; AVX512BW-LABEL: vec512_i8_signed_reg_reg:741; AVX512BW: # %bb.0:742; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k1743; AVX512BW-NEXT: vpminsb %zmm1, %zmm0, %zmm2744; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm1745; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1746; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1747; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1748; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2749; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1 {%k1}750; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0751; AVX512BW-NEXT: retq752 %t3 = icmp sgt <64 x i8> %a1, %a2 ; signed753 %t4 = select <64 x i1> %t3, <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>754 %t5 = select <64 x i1> %t3, <64 x i8> %a2, <64 x i8> %a1755 %t6 = select <64 x i1> %t3, <64 x i8> %a1, <64 x i8> %a2756 %t7 = sub <64 x i8> %t6, %t5757 %t8 = lshr <64 x i8> %t7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>758 %t9 = mul nsw <64 x i8> %t8, %t4 ; signed759 %a10 = add nsw <64 x i8> %t9, %a1 ; signed760 ret <64 x i8> %a10761}762 763define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwind {764; AVX512F-LABEL: vec512_i8_unsigned_reg_reg:765; AVX512F: # %bb.0:766; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2767; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3768; AVX512F-NEXT: vpminub %ymm2, %ymm3, %ymm4769; AVX512F-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5770; AVX512F-NEXT: vpminub %ymm1, %ymm0, %ymm6771; AVX512F-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7772; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5773; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1774; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1775; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2776; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2777; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2778; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]779; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2780; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1781; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1782; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4783; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6784; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2785; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1786; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1787; AVX512F-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 ^ (zmm5 & (zmm1 ^ zmm4))788; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2789; AVX512F-NEXT: vpaddb %ymm3, %ymm2, %ymm2790; AVX512F-NEXT: vpaddb %ymm0, %ymm1, %ymm0791; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0792; AVX512F-NEXT: retq793;794; AVX512VL-FALLBACK-LABEL: vec512_i8_unsigned_reg_reg:795; AVX512VL-FALLBACK: # %bb.0:796; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2797; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm3798; AVX512VL-FALLBACK-NEXT: vpminub %ymm2, %ymm3, %ymm4799; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5800; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm6801; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7802; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5803; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1804; AVX512VL-FALLBACK-NEXT: vpsubb %ymm6, %ymm1, %ymm1805; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2806; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2807; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2808; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]809; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm2, %ymm2810; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1811; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm1, %ymm1812; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4813; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6814; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2815; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1816; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1817; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm1 = zmm1 ^ (zmm5 & (zmm1 ^ zmm4))818; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2819; AVX512VL-FALLBACK-NEXT: vpaddb %ymm3, %ymm2, %ymm2820; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm1, %ymm0821; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0822; AVX512VL-FALLBACK-NEXT: retq823;824; AVX512BW-LABEL: vec512_i8_unsigned_reg_reg:825; AVX512BW: # %bb.0:826; AVX512BW-NEXT: vpcmpnleub %zmm1, %zmm0, %k1827; AVX512BW-NEXT: vpminub %zmm1, %zmm0, %zmm2828; AVX512BW-NEXT: vpmaxub %zmm1, %zmm0, %zmm1829; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm1830; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm1831; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1832; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2833; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1 {%k1}834; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm0835; AVX512BW-NEXT: retq836 %t3 = icmp ugt <64 x i8> %a1, %a2837 %t4 = select <64 x i1> %t3, <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>838 %t5 = select <64 x i1> %t3, <64 x i8> %a2, <64 x i8> %a1839 %t6 = select <64 x i1> %t3, <64 x i8> %a1, <64 x i8> %a2840 %t7 = sub <64 x i8> %t6, %t5841 %t8 = lshr <64 x i8> %t7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>842 %t9 = mul <64 x i8> %t8, %t4843 %a10 = add <64 x i8> %t9, %a1844 ret <64 x i8> %a10845}846 847; Values are loaded. Only check signed case.848 849define <64 x i8> @vec512_i8_signed_mem_reg(ptr %a1_addr, <64 x i8> %a2) nounwind {850; AVX512F-LABEL: vec512_i8_signed_mem_reg:851; AVX512F: # %bb.0:852; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1853; AVX512F-NEXT: vmovdqa (%rdi), %ymm2854; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm3855; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm3, %ymm4856; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm5857; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4858; AVX512F-NEXT: vpminsb %ymm1, %ymm3, %ymm5859; AVX512F-NEXT: vpmaxsb %ymm1, %ymm3, %ymm1860; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1861; AVX512F-NEXT: vpminsb %ymm0, %ymm2, %ymm5862; AVX512F-NEXT: vpmaxsb %ymm0, %ymm2, %ymm0863; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm0864; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm0865; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1866; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5867; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]868; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5869; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1870; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7871; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1872; AVX512F-NEXT: vpand %ymm6, %ymm0, %ymm0873; AVX512F-NEXT: vpsubb %ymm0, %ymm7, %ymm0874; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0875; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))876; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1877; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm1878; AVX512F-NEXT: vpaddb %ymm2, %ymm0, %ymm0879; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0880; AVX512F-NEXT: retq881;882; AVX512VL-FALLBACK-LABEL: vec512_i8_signed_mem_reg:883; AVX512VL-FALLBACK: # %bb.0:884; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1885; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm2886; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm3887; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm3, %ymm4888; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm5889; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4890; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm3, %ymm5891; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm3, %ymm1892; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1893; AVX512VL-FALLBACK-NEXT: vpminsb %ymm0, %ymm2, %ymm5894; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm0, %ymm2, %ymm0895; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm0, %ymm0896; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm0897; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1898; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm5899; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]900; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm5901; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1902; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7903; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1904; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm0, %ymm0905; AVX512VL-FALLBACK-NEXT: vpsubb %ymm0, %ymm7, %ymm0906; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0907; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))908; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1909; AVX512VL-FALLBACK-NEXT: vpaddb %ymm3, %ymm1, %ymm1910; AVX512VL-FALLBACK-NEXT: vpaddb %ymm2, %ymm0, %ymm0911; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0912; AVX512VL-FALLBACK-NEXT: retq913;914; AVX512BW-LABEL: vec512_i8_signed_mem_reg:915; AVX512BW: # %bb.0:916; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm1917; AVX512BW-NEXT: vpcmpgtb %zmm0, %zmm1, %k1918; AVX512BW-NEXT: vpminsb %zmm0, %zmm1, %zmm2919; AVX512BW-NEXT: vpmaxsb %zmm0, %zmm1, %zmm0920; AVX512BW-NEXT: vpsubb %zmm2, %zmm0, %zmm0921; AVX512BW-NEXT: vpsrlw $1, %zmm0, %zmm0922; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0923; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2924; AVX512BW-NEXT: vpsubb %zmm0, %zmm2, %zmm0 {%k1}925; AVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0926; AVX512BW-NEXT: retq927 %a1 = load <64 x i8>, ptr %a1_addr928 %t3 = icmp sgt <64 x i8> %a1, %a2 ; signed929 %t4 = select <64 x i1> %t3, <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>930 %t5 = select <64 x i1> %t3, <64 x i8> %a2, <64 x i8> %a1931 %t6 = select <64 x i1> %t3, <64 x i8> %a1, <64 x i8> %a2932 %t7 = sub <64 x i8> %t6, %t5933 %t8 = lshr <64 x i8> %t7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>934 %t9 = mul nsw <64 x i8> %t8, %t4 ; signed935 %a10 = add nsw <64 x i8> %t9, %a1 ; signed936 ret <64 x i8> %a10937}938 939define <64 x i8> @vec512_i8_signed_reg_mem(<64 x i8> %a1, ptr %a2_addr) nounwind {940; AVX512F-LABEL: vec512_i8_signed_reg_mem:941; AVX512F: # %bb.0:942; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1943; AVX512F-NEXT: vmovdqa (%rdi), %ymm2944; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm3945; AVX512F-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm4946; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm5947; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4948; AVX512F-NEXT: vpminsb %ymm3, %ymm1, %ymm5949; AVX512F-NEXT: vpmaxsb %ymm3, %ymm1, %ymm3950; AVX512F-NEXT: vpsubb %ymm5, %ymm3, %ymm3951; AVX512F-NEXT: vpminsb %ymm2, %ymm0, %ymm5952; AVX512F-NEXT: vpmaxsb %ymm2, %ymm0, %ymm2953; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2954; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2955; AVX512F-NEXT: vpsrlw $1, %ymm3, %ymm3956; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm5957; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]958; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5959; AVX512F-NEXT: vpand %ymm6, %ymm3, %ymm3960; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7961; AVX512F-NEXT: vpsubb %ymm3, %ymm7, %ymm3962; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2963; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2964; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2965; AVX512F-NEXT: vpternlogq {{.*#+}} zmm2 = zmm5 ^ (zmm4 & (zmm2 ^ zmm5))966; AVX512F-NEXT: vextracti64x4 $1, %zmm2, %ymm3967; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1968; AVX512F-NEXT: vpaddb %ymm0, %ymm2, %ymm0969; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0970; AVX512F-NEXT: retq971;972; AVX512VL-FALLBACK-LABEL: vec512_i8_signed_reg_mem:973; AVX512VL-FALLBACK: # %bb.0:974; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm1975; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm2976; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm3977; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm3, %ymm1, %ymm4978; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm5979; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4980; AVX512VL-FALLBACK-NEXT: vpminsb %ymm3, %ymm1, %ymm5981; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm3, %ymm1, %ymm3982; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm3, %ymm3983; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm0, %ymm5984; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm0, %ymm2985; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2986; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2987; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm3, %ymm3988; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm5989; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]990; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm5991; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm3, %ymm3992; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7993; AVX512VL-FALLBACK-NEXT: vpsubb %ymm3, %ymm7, %ymm3994; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2995; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2996; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2997; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm2 = zmm5 ^ (zmm4 & (zmm2 ^ zmm5))998; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm2, %ymm3999; AVX512VL-FALLBACK-NEXT: vpaddb %ymm1, %ymm3, %ymm11000; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm2, %ymm01001; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm01002; AVX512VL-FALLBACK-NEXT: retq1003;1004; AVX512BW-LABEL: vec512_i8_signed_reg_mem:1005; AVX512BW: # %bb.0:1006; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm11007; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k11008; AVX512BW-NEXT: vpminsb %zmm1, %zmm0, %zmm21009; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm11010; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm11011; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm11012; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm11013; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm21014; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1 {%k1}1015; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm01016; AVX512BW-NEXT: retq1017 %a2 = load <64 x i8>, ptr %a2_addr1018 %t3 = icmp sgt <64 x i8> %a1, %a2 ; signed1019 %t4 = select <64 x i1> %t3, <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1020 %t5 = select <64 x i1> %t3, <64 x i8> %a2, <64 x i8> %a11021 %t6 = select <64 x i1> %t3, <64 x i8> %a1, <64 x i8> %a21022 %t7 = sub <64 x i8> %t6, %t51023 %t8 = lshr <64 x i8> %t7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1024 %t9 = mul nsw <64 x i8> %t8, %t4 ; signed1025 %a10 = add nsw <64 x i8> %t9, %a1 ; signed1026 ret <64 x i8> %a101027}1028 1029define <64 x i8> @vec512_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {1030; AVX512F-LABEL: vec512_i8_signed_mem_mem:1031; AVX512F: # %bb.0:1032; AVX512F-NEXT: vmovdqa (%rsi), %ymm01033; AVX512F-NEXT: vmovdqa 32(%rsi), %ymm11034; AVX512F-NEXT: vmovdqa (%rdi), %ymm21035; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm31036; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm3, %ymm41037; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm51038; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm41039; AVX512F-NEXT: vpminsb %ymm1, %ymm3, %ymm51040; AVX512F-NEXT: vpmaxsb %ymm1, %ymm3, %ymm11041; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm11042; AVX512F-NEXT: vpminsb %ymm0, %ymm2, %ymm51043; AVX512F-NEXT: vpmaxsb %ymm0, %ymm2, %ymm01044; AVX512F-NEXT: vpsubb %ymm5, %ymm0, %ymm01045; AVX512F-NEXT: vpsrlw $1, %ymm0, %ymm01046; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm11047; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm51048; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]1049; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm51050; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm11051; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm71052; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm11053; AVX512F-NEXT: vpand %ymm6, %ymm0, %ymm01054; AVX512F-NEXT: vpsubb %ymm0, %ymm7, %ymm01055; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm01056; AVX512F-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))1057; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm11058; AVX512F-NEXT: vpaddb %ymm3, %ymm1, %ymm11059; AVX512F-NEXT: vpaddb %ymm2, %ymm0, %ymm01060; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm01061; AVX512F-NEXT: retq1062;1063; AVX512VL-FALLBACK-LABEL: vec512_i8_signed_mem_mem:1064; AVX512VL-FALLBACK: # %bb.0:1065; AVX512VL-FALLBACK-NEXT: vmovdqa (%rsi), %ymm01066; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rsi), %ymm11067; AVX512VL-FALLBACK-NEXT: vmovdqa (%rdi), %ymm21068; AVX512VL-FALLBACK-NEXT: vmovdqa 32(%rdi), %ymm31069; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm3, %ymm41070; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm51071; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm41072; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm3, %ymm51073; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm3, %ymm11074; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm11075; AVX512VL-FALLBACK-NEXT: vpminsb %ymm0, %ymm2, %ymm51076; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm0, %ymm2, %ymm01077; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm0, %ymm01078; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm0, %ymm01079; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm11080; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm51081; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]1082; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm51083; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm11084; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm71085; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm11086; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm0, %ymm01087; AVX512VL-FALLBACK-NEXT: vpsubb %ymm0, %ymm7, %ymm01088; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm01089; AVX512VL-FALLBACK-NEXT: vpternlogq {{.*#+}} zmm0 = zmm5 ^ (zmm4 & (zmm0 ^ zmm5))1090; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm0, %ymm11091; AVX512VL-FALLBACK-NEXT: vpaddb %ymm3, %ymm1, %ymm11092; AVX512VL-FALLBACK-NEXT: vpaddb %ymm2, %ymm0, %ymm01093; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm01094; AVX512VL-FALLBACK-NEXT: retq1095;1096; AVX512BW-LABEL: vec512_i8_signed_mem_mem:1097; AVX512BW: # %bb.0:1098; AVX512BW-NEXT: vmovdqa64 (%rdi), %zmm01099; AVX512BW-NEXT: vmovdqa64 (%rsi), %zmm11100; AVX512BW-NEXT: vpcmpgtb %zmm1, %zmm0, %k11101; AVX512BW-NEXT: vpminsb %zmm1, %zmm0, %zmm21102; AVX512BW-NEXT: vpmaxsb %zmm1, %zmm0, %zmm11103; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm11104; AVX512BW-NEXT: vpsrlw $1, %zmm1, %zmm11105; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm11106; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm21107; AVX512BW-NEXT: vpsubb %zmm1, %zmm2, %zmm1 {%k1}1108; AVX512BW-NEXT: vpaddb %zmm0, %zmm1, %zmm01109; AVX512BW-NEXT: retq1110 %a1 = load <64 x i8>, ptr %a1_addr1111 %a2 = load <64 x i8>, ptr %a2_addr1112 %t3 = icmp sgt <64 x i8> %a1, %a2 ; signed1113 %t4 = select <64 x i1> %t3, <64 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <64 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1114 %t5 = select <64 x i1> %t3, <64 x i8> %a2, <64 x i8> %a11115 %t6 = select <64 x i1> %t3, <64 x i8> %a1, <64 x i8> %a21116 %t7 = sub <64 x i8> %t6, %t51117 %t8 = lshr <64 x i8> %t7, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>1118 %t9 = mul nsw <64 x i8> %t8, %t4 ; signed1119 %a10 = add nsw <64 x i8> %t9, %a1 ; signed1120 ret <64 x i8> %a101121}1122