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1; REQUIRES: asserts2; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3;4; Test scheduling of copy instructions.5;6; Argument copies should be hoisted to the top of the block.7; Return copies should be sunk to the end.8; MUL_HiLo PhysReg use copies should be just above the mul.9; MUL_HiLo PhysReg def copies should be just below the mul.10;11; CHECK: *** Final schedule for %bb.1 ***12; CHECK: $eax = COPY13; CHECK-NEXT: MUL32r %{{[0-9]+}}:gr32, implicit-def $eax, implicit-def $edx, implicit-def dead $eflags, implicit $eax14; CHECK-NEXT: COPY $e{{[ad]}}x15; CHECK-NEXT: COPY $e{{[ad]}}x16; CHECK: DIVSSrm17define i64 @mulhoist(i32 %a, i32 %b) #0 {18entry:19 br label %body20 21body:22 %convb = sitofp i32 %b to float23 ; Generates an iMUL64r to legalize types.24 %aa = zext i32 %a to i6425 %mul = mul i64 %aa, 7438326 ; Do some dependent long latency stuff.27 %trunc = trunc i64 %mul to i3228 %convm = sitofp i32 %trunc to float29 %divm = fdiv float %convm, 0.7530 ;%addmb = fadd float %divm, %convb31 ;%divmb = fdiv float %addmb, 0.12532 ; Do some independent long latency stuff.33 %conva = sitofp i32 %a to float34 %diva = fdiv float %conva, 0.7535 %addab = fadd float %diva, %convb36 %divab = fdiv float %addab, 0.12537 br label %end38 39end:40 %val = fptosi float %divab to i6441 %add = add i64 %mul, %val42 ret i64 %add43}44 45attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" }46 47!0 = !{!"float", !1}48!1 = !{!"omnipotent char", !2}49!2 = !{!"Simple C/C++ TBAA"}50