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1; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -x86-early-ifcvt -enable-misched \2; RUN:          -misched=shuffle -misched-prera-direction=bottomup -verify-machineinstrs \3; RUN:     | FileCheck %s4; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -x86-early-ifcvt -enable-misched \5; RUN:          -misched=shuffle -misched-prera-direction=topdown -verify-machineinstrs \6; RUN:     | FileCheck %s --check-prefix TOPDOWN7; REQUIRES: asserts8;9; Interesting MachineScheduler cases.10;11; FIXME: There should be an assert in the coalescer that we're not rematting12; "not-quite-dead" copies, but that breaks a lot of tests <rdar://problem/11148682>.13 14declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind15 16; From oggenc.17; After coalescing, we have a dead superreg (RAX) definition.18;19; CHECK: xorl %esi, %esi20; CHECK: movl $32, %ecx21; CHECK: rep;movsl22define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {23entry:24  br i1 undef, label %for.cond.preheader, label %if.end25 26for.cond.preheader:                               ; preds = %entry27  call void @llvm.memcpy.p0.p0.i64(ptr align 4 undef, ptr align 4 null, i64 128, i1 false) nounwind28  unreachable29 30if.end:                                           ; preds = %entry31  ret void32}33 34; The machine verifier checks that EFLAGS kill flags are updated when35; the scheduler reorders cmovel instructions.36;37; CHECK: test38; CHECK: cmovel39; CHECK: cmovel40; CHECK: call41define void @foo(i32 %b) nounwind uwtable ssp {42entry:43  %tobool = icmp ne i32 %b, 044  br i1 %tobool, label %if.then, label %if.end45 46if.then:                                          ; preds = %entry47  br label %if.end48 49if.end:                                           ; preds = %if.then, %entry50  %v1 = phi i32 [1, %entry], [2, %if.then]51  %v2 = phi i32 [3, %entry], [4, %if.then]52  call void @bar(i32 %v1, i32 %v2)53  ret void54}55 56declare void @bar(i32,i32)57 58; Test that the DAG builder can handle an undef vreg on ExitSU.59; CHECK: hasundef60; CHECK: call61 62%t0 = type { i32, i32, i8 }63%t6 = type { ptr, ptr }64%t7 = type { ptr }65 66define void @hasundef() unnamed_addr uwtable ssp align 2 {67  %1 = alloca %t0, align 868  br i1 undef, label %3, label %269 70; <label>:2                                       ; preds = %071  unreachable72 73; <label>:3                                       ; preds = %074  br i1 undef, label %4, label %575 76; <label>:4                                       ; preds = %377  call void undef(ptr undef, ptr %1)78  unreachable79 80; <label>:5                                       ; preds = %381  ret void82}83 84; Test top-down subregister liveness tracking. Self-verification85; catches any pressure set underflow.86; rdar://12797931.87;88; TOPDOWN: @testSubregTracking89; TOPDOWN: divb90; TOPDOWN: movzbl %al91; TOPDOWN: ret92define void @testSubregTracking() nounwind uwtable ssp align 2 {93  %tmp = load i8, ptr undef, align 194  %tmp6 = sub i8 0, %tmp95  %tmp7 = load i8, ptr undef, align 196  %tmp8 = udiv i8 %tmp6, %tmp797  %tmp9 = zext i8 %tmp8 to i6498  %tmp10 = load i8, ptr undef, align 199  %tmp11 = zext i8 %tmp10 to i64100  %tmp12 = mul i64 %tmp11, %tmp9101  %tmp13 = urem i8 %tmp6, %tmp7102  %tmp14 = zext i8 %tmp13 to i32103  %tmp15 = add nsw i32 %tmp14, 0104  %tmp16 = add i32 %tmp15, 0105  store i32 %tmp16, ptr undef, align 4106  %tmp17 = add i64 0, %tmp12107  store i64 %tmp17, ptr undef, align 8108  ret void109}110