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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s3 4define i64 @t0(ptr %p) {5; CHECK-LABEL: t0:6; CHECK: ## %bb.0:7; CHECK-NEXT: movq (%rdi), %mm08; CHECK-NEXT: paddq %mm0, %mm09; CHECK-NEXT: movq %mm0, %rax10; CHECK-NEXT: retq11 %t = load <1 x i64>, ptr %p12 %u = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %t, <1 x i64> %t)13 %s = bitcast <1 x i64> %u to i6414 ret i64 %s15}16 17define i64 @t1(ptr %p) {18; CHECK-LABEL: t1:19; CHECK: ## %bb.0:20; CHECK-NEXT: movq (%rdi), %mm021; CHECK-NEXT: paddd %mm0, %mm022; CHECK-NEXT: movq %mm0, %rax23; CHECK-NEXT: retq24 %t = load <1 x i64>, ptr %p25 %u = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %t, <1 x i64> %t)26 %s = bitcast <1 x i64> %u to i6427 ret i64 %s28}29 30define i64 @t2(ptr %p) {31; CHECK-LABEL: t2:32; CHECK: ## %bb.0:33; CHECK-NEXT: movq (%rdi), %mm034; CHECK-NEXT: paddw %mm0, %mm035; CHECK-NEXT: movq %mm0, %rax36; CHECK-NEXT: retq37 %t = load <1 x i64>, ptr %p38 %u = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %t, <1 x i64> %t)39 %s = bitcast <1 x i64> %u to i6440 ret i64 %s41}42 43define i64 @t3(ptr %p) {44; CHECK-LABEL: t3:45; CHECK: ## %bb.0:46; CHECK-NEXT: movq (%rdi), %mm047; CHECK-NEXT: paddb %mm0, %mm048; CHECK-NEXT: movq %mm0, %rax49; CHECK-NEXT: retq50 %t = load <1 x i64>, ptr %p51 %u = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> %t, <1 x i64> %t)52 %s = bitcast <1 x i64> %u to i6453 ret i64 %s54}55 56@R = external global <1 x i64>57 58define void @t4(<1 x i64> %A, <1 x i64> %B) {59; CHECK-LABEL: t4:60; CHECK: ## %bb.0: ## %entry61; CHECK-NEXT: movq %rsi, %mm062; CHECK-NEXT: movq %rdi, %mm163; CHECK-NEXT: paddusw %mm0, %mm164; CHECK-NEXT: movq _R@GOTPCREL(%rip), %rax65; CHECK-NEXT: movq %mm1, (%rax)66; CHECK-NEXT: emms67; CHECK-NEXT: retq68entry:69 %tmp7 = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> %A, <1 x i64> %B)70 store <1 x i64> %tmp7, ptr @R71 tail call void @llvm.x86.mmx.emms()72 ret void73}74 75define i64 @t5(i32 %a, i32 %b) nounwind readnone {76; CHECK-LABEL: t5:77; CHECK: ## %bb.0:78; CHECK-NEXT: movd %esi, %xmm079; CHECK-NEXT: movd %edi, %xmm180; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]81; CHECK-NEXT: movq %xmm1, %rax82; CHECK-NEXT: retq83 %v0 = insertelement <2 x i32> undef, i32 %a, i32 084 %v1 = insertelement <2 x i32> %v0, i32 %b, i32 185 %conv = bitcast <2 x i32> %v1 to i6486 ret i64 %conv87}88 89declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)90 91define <1 x i64> @t6(i64 %t) {92; CHECK-LABEL: t6:93; CHECK: ## %bb.0:94; CHECK-NEXT: movq %rdi, %mm095; CHECK-NEXT: psllq $48, %mm096; CHECK-NEXT: movq %mm0, %rax97; CHECK-NEXT: retq98 %t1 = insertelement <1 x i64> undef, i64 %t, i32 099 %t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48)100 ret <1 x i64> %t2101}102 103declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>)104declare <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64>, <1 x i64>)105declare <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64>, <1 x i64>)106declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>)107declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>)108declare void @llvm.x86.mmx.emms()109 110