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1; RUN: not llc -mtriple=x86_64-unknown-unknown -relocation-model=pic %s -o /dev/null 2>&1 | FileCheck %s2 3; Tests come from "clang/test/CodeGen/ms-inline-asm-variables.c"4;5; int gVar;6; void t1() {7; __asm add ecx, dword ptr gVar[4590 + rax + rcx*4]8; __asm add dword ptr [gVar + rax + 45 + 23 - 53 + 60 - 2 + rcx*8], ecx9; __asm add 1 + 1 + 2 + 3[gVar + rcx + rbx], eax10; gVar = 3;11; }12 13@gVar = global i32 0, align 414 15; Function Attrs: noinline nounwind optnone uwtable16define void @t1() #0 {17; CHECK: error: Don't use 2 or more regs for mem offset in PIC model18; CHECK: error: Don't use 2 or more regs for mem offset in PIC model19; CHECK: error: Don't use 2 or more regs for mem offset in PIC model20entry:21 call void asm sideeffect inteldialect "add ecx, dword ptr ${2:P}[rax + rcx * $$4 + $$4590]\0A\09add dword ptr ${0:P}[rcx + rcx * $$8 + $$73], ecx\0A\09add ${1:P}[rcx + rbx + $$7], eax", "=*m,=*m,*m,~{ecx},~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar)22 store i32 3, ptr @gVar, align 423 ret void24}25 26attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }27attributes #1 = { nounwind }28 29!llvm.module.flags = !{!0}30 31!0 = !{i32 1, !"wchar_size", i32 4}32