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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=+false-deps-mulc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=ENABLE3; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=-false-deps-mulc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=DISABLE4 5define <16 x float> @fmulcph(<16 x float> %a0, <16 x float> %a1) {6; ENABLE-LABEL: fmulcph:7; ENABLE: # %bb.0:8; ENABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill9; ENABLE-NEXT: #APP10; ENABLE-NEXT: nop11; ENABLE-NEXT: #NO_APP12; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload13; ENABLE-NEXT: vpxor %xmm2, %xmm2, %xmm214; ENABLE-NEXT: vfmulcph %zmm1, %zmm0, %zmm215; ENABLE-NEXT: vmovaps %zmm2, %zmm016; ENABLE-NEXT: retq17;18; DISABLE-LABEL: fmulcph:19; DISABLE: # %bb.0:20; DISABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill21; DISABLE-NEXT: #APP22; DISABLE-NEXT: nop23; DISABLE-NEXT: #NO_APP24; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 # 64-byte Folded Reload25; DISABLE-NEXT: vmovaps %zmm2, %zmm026; DISABLE-NEXT: retq27 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()28 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)29 ret <16 x float> %230}31 32define <16 x float> @fmulcph_mem(<16 x float> %a0, ptr %p1) {33; ENABLE-LABEL: fmulcph_mem:34; ENABLE: # %bb.0:35; ENABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill36; ENABLE-NEXT: #APP37; ENABLE-NEXT: nop38; ENABLE-NEXT: #NO_APP39; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload40; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm141; ENABLE-NEXT: vfmulcph (%rdi), %zmm0, %zmm142; ENABLE-NEXT: vmovaps %zmm1, %zmm043; ENABLE-NEXT: retq44;45; DISABLE-LABEL: fmulcph_mem:46; DISABLE: # %bb.0:47; DISABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill48; DISABLE-NEXT: #APP49; DISABLE-NEXT: nop50; DISABLE-NEXT: #NO_APP51; DISABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload52; DISABLE-NEXT: vfmulcph (%rdi), %zmm0, %zmm153; DISABLE-NEXT: vmovaps %zmm1, %zmm054; DISABLE-NEXT: retq55 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()56 %a1 = load <16 x float>, ptr %p1, align 6457 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)58 ret <16 x float> %259}60 61define <16 x float> @fmulcph_broadcast(<16 x float> %a0, ptr %p1) {62; ENABLE-LABEL: fmulcph_broadcast:63; ENABLE: # %bb.0:64; ENABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill65; ENABLE-NEXT: #APP66; ENABLE-NEXT: nop67; ENABLE-NEXT: #NO_APP68; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload69; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm170; ENABLE-NEXT: vfmulcph (%rdi){1to16}, %zmm0, %zmm171; ENABLE-NEXT: vmovaps %zmm1, %zmm072; ENABLE-NEXT: retq73;74; DISABLE-LABEL: fmulcph_broadcast:75; DISABLE: # %bb.0:76; DISABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill77; DISABLE-NEXT: #APP78; DISABLE-NEXT: nop79; DISABLE-NEXT: #NO_APP80; DISABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload81; DISABLE-NEXT: vfmulcph (%rdi){1to16}, %zmm0, %zmm182; DISABLE-NEXT: vmovaps %zmm1, %zmm083; DISABLE-NEXT: retq84 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()85 %v1 = load float, ptr %p1, align 486 %t0 = insertelement <16 x float> undef, float %v1, i64 087 %a1 = shufflevector <16 x float> %t0, <16 x float> undef, <16 x i32> zeroinitializer88 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)89 ret <16 x float> %290}91 92define <16 x float> @fmulcph_maskz(<16 x float> %a0, <16 x float> %a1, ptr %mask) {93; ENABLE-LABEL: fmulcph_maskz:94; ENABLE: # %bb.0:95; ENABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill96; ENABLE-NEXT: #APP97; ENABLE-NEXT: nop98; ENABLE-NEXT: #NO_APP99; ENABLE-NEXT: kmovw (%rdi), %k1100; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload101; ENABLE-NEXT: vpxor %xmm2, %xmm2, %xmm2102; ENABLE-NEXT: vfmulcph %zmm1, %zmm0, %zmm2 {%k1} {z}103; ENABLE-NEXT: vmovaps %zmm2, %zmm0104; ENABLE-NEXT: retq105;106; DISABLE-LABEL: fmulcph_maskz:107; DISABLE: # %bb.0:108; DISABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill109; DISABLE-NEXT: #APP110; DISABLE-NEXT: nop111; DISABLE-NEXT: #NO_APP112; DISABLE-NEXT: kmovw (%rdi), %k1113; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 {%k1} {z} # 64-byte Folded Reload114; DISABLE-NEXT: vmovaps %zmm2, %zmm0115; DISABLE-NEXT: retq116 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()117 %2 = load i16, ptr %mask118 %3 = call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> zeroinitializer, i16 %2, i32 4)119 ret <16 x float> %3120}121 122define <16 x float> @fcmulcph(<16 x float> %a0, <16 x float> %a1) {123; ENABLE-LABEL: fcmulcph:124; ENABLE: # %bb.0:125; ENABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill126; ENABLE-NEXT: #APP127; ENABLE-NEXT: nop128; ENABLE-NEXT: #NO_APP129; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload130; ENABLE-NEXT: vpxor %xmm2, %xmm2, %xmm2131; ENABLE-NEXT: vfcmulcph %zmm1, %zmm0, %zmm2132; ENABLE-NEXT: vmovaps %zmm2, %zmm0133; ENABLE-NEXT: retq134;135; DISABLE-LABEL: fcmulcph:136; DISABLE: # %bb.0:137; DISABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill138; DISABLE-NEXT: #APP139; DISABLE-NEXT: nop140; DISABLE-NEXT: #NO_APP141; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 # 64-byte Folded Reload142; DISABLE-NEXT: vmovaps %zmm2, %zmm0143; DISABLE-NEXT: retq144 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()145 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)146 ret <16 x float> %2147}148 149define <16 x float> @fcmulcph_mem(<16 x float> %a0, ptr %p1) {150; ENABLE-LABEL: fcmulcph_mem:151; ENABLE: # %bb.0:152; ENABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill153; ENABLE-NEXT: #APP154; ENABLE-NEXT: nop155; ENABLE-NEXT: #NO_APP156; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload157; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm1158; ENABLE-NEXT: vfcmulcph (%rdi), %zmm0, %zmm1159; ENABLE-NEXT: vmovaps %zmm1, %zmm0160; ENABLE-NEXT: retq161;162; DISABLE-LABEL: fcmulcph_mem:163; DISABLE: # %bb.0:164; DISABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill165; DISABLE-NEXT: #APP166; DISABLE-NEXT: nop167; DISABLE-NEXT: #NO_APP168; DISABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload169; DISABLE-NEXT: vfcmulcph (%rdi), %zmm0, %zmm1170; DISABLE-NEXT: vmovaps %zmm1, %zmm0171; DISABLE-NEXT: retq172 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()173 %a1 = load <16 x float>, ptr %p1, align 64174 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)175 ret <16 x float> %2176}177 178define <16 x float> @fcmulcph_broadcast(<16 x float> %a0, ptr %p1) {179; ENABLE-LABEL: fcmulcph_broadcast:180; ENABLE: # %bb.0:181; ENABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill182; ENABLE-NEXT: #APP183; ENABLE-NEXT: nop184; ENABLE-NEXT: #NO_APP185; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload186; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm1187; ENABLE-NEXT: vfcmulcph (%rdi){1to16}, %zmm0, %zmm1188; ENABLE-NEXT: vmovaps %zmm1, %zmm0189; ENABLE-NEXT: retq190;191; DISABLE-LABEL: fcmulcph_broadcast:192; DISABLE: # %bb.0:193; DISABLE-NEXT: vmovups %zmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill194; DISABLE-NEXT: #APP195; DISABLE-NEXT: nop196; DISABLE-NEXT: #NO_APP197; DISABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm0 # 64-byte Reload198; DISABLE-NEXT: vfcmulcph (%rdi){1to16}, %zmm0, %zmm1199; DISABLE-NEXT: vmovaps %zmm1, %zmm0200; DISABLE-NEXT: retq201 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()202 %v1 = load float, ptr %p1, align 4203 %t0 = insertelement <16 x float> undef, float %v1, i64 0204 %a1 = shufflevector <16 x float> %t0, <16 x float> undef, <16 x i32> zeroinitializer205 %2 = call <16 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> undef, i16 -1, i32 4)206 ret <16 x float> %2207}208 209define <16 x float> @fcmulcph_maskz(<16 x float> %a0, <16 x float> %a1, ptr %mask) {210; ENABLE-LABEL: fcmulcph_maskz:211; ENABLE: # %bb.0:212; ENABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill213; ENABLE-NEXT: #APP214; ENABLE-NEXT: nop215; ENABLE-NEXT: #NO_APP216; ENABLE-NEXT: kmovw (%rdi), %k1217; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %zmm1 # 64-byte Reload218; ENABLE-NEXT: vpxor %xmm2, %xmm2, %xmm2219; ENABLE-NEXT: vfcmulcph %zmm1, %zmm0, %zmm2 {%k1} {z}220; ENABLE-NEXT: vmovaps %zmm2, %zmm0221; ENABLE-NEXT: retq222;223; DISABLE-LABEL: fcmulcph_maskz:224; DISABLE: # %bb.0:225; DISABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill226; DISABLE-NEXT: #APP227; DISABLE-NEXT: nop228; DISABLE-NEXT: #NO_APP229; DISABLE-NEXT: kmovw (%rdi), %k1230; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm2 {%k1} {z} # 64-byte Folded Reload231; DISABLE-NEXT: vmovaps %zmm2, %zmm0232; DISABLE-NEXT: retq233 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()234 %2 = load i16, ptr %mask235 %3 = call <16 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.512(<16 x float> %a0, <16 x float> %a1, <16 x float> zeroinitializer, i16 %2, i32 4)236 ret <16 x float> %3237}238 239define <4 x float> @fmulc(<4 x float> %a0, <4 x float> %a1) {240; ENABLE-LABEL: fmulc:241; ENABLE: # %bb.0:242; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill243; ENABLE-NEXT: #APP244; ENABLE-NEXT: nop245; ENABLE-NEXT: #NO_APP246; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload247; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2248; ENABLE-NEXT: vfmulcph %xmm1, %xmm0, %xmm2249; ENABLE-NEXT: vmovaps %xmm2, %xmm0250; ENABLE-NEXT: retq251;252; DISABLE-LABEL: fmulc:253; DISABLE: # %bb.0:254; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill255; DISABLE-NEXT: #APP256; DISABLE-NEXT: nop257; DISABLE-NEXT: #NO_APP258; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 # 16-byte Folded Reload259; DISABLE-NEXT: vmovaps %xmm2, %xmm0260; DISABLE-NEXT: retq261 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()262 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)263 ret <4 x float> %2264}265 266define <4 x float> @fmulc_mem(<4 x float> %a0, ptr %p1) {267; ENABLE-LABEL: fmulc_mem:268; ENABLE: # %bb.0:269; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill270; ENABLE-NEXT: #APP271; ENABLE-NEXT: nop272; ENABLE-NEXT: #NO_APP273; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload274; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1275; ENABLE-NEXT: vfmulcph (%rdi), %xmm0, %xmm1276; ENABLE-NEXT: vmovaps %xmm1, %xmm0277; ENABLE-NEXT: retq278;279; DISABLE-LABEL: fmulc_mem:280; DISABLE: # %bb.0:281; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill282; DISABLE-NEXT: #APP283; DISABLE-NEXT: nop284; DISABLE-NEXT: #NO_APP285; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload286; DISABLE-NEXT: vfmulcph (%rdi), %xmm0, %xmm1287; DISABLE-NEXT: vmovaps %xmm1, %xmm0288; DISABLE-NEXT: retq289 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()290 %a1 = load <4 x float>, ptr %p1, align 64291 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)292 ret <4 x float> %2293}294 295define <4 x float> @fmulc_broadcast(<4 x float> %a0, ptr %p1) {296; ENABLE-LABEL: fmulc_broadcast:297; ENABLE: # %bb.0:298; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill299; ENABLE-NEXT: #APP300; ENABLE-NEXT: nop301; ENABLE-NEXT: #NO_APP302; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload303; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1304; ENABLE-NEXT: vfmulcph (%rdi){1to4}, %xmm0, %xmm1305; ENABLE-NEXT: vmovaps %xmm1, %xmm0306; ENABLE-NEXT: retq307;308; DISABLE-LABEL: fmulc_broadcast:309; DISABLE: # %bb.0:310; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill311; DISABLE-NEXT: #APP312; DISABLE-NEXT: nop313; DISABLE-NEXT: #NO_APP314; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload315; DISABLE-NEXT: vfmulcph (%rdi){1to4}, %xmm0, %xmm1316; DISABLE-NEXT: vmovaps %xmm1, %xmm0317; DISABLE-NEXT: retq318 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()319 %v1 = load float, ptr %p1, align 4320 %t0 = insertelement <4 x float> undef, float %v1, i64 0321 %a1 = shufflevector <4 x float> %t0, <4 x float> undef, <4 x i32> zeroinitializer322 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)323 ret <4 x float> %2324}325 326define <4 x float> @fmulc_maskz(<4 x float> %a0, <4 x float> %a1, ptr %mask) {327; ENABLE-LABEL: fmulc_maskz:328; ENABLE: # %bb.0:329; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill330; ENABLE-NEXT: #APP331; ENABLE-NEXT: nop332; ENABLE-NEXT: #NO_APP333; ENABLE-NEXT: kmovb (%rdi), %k1334; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload335; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2336; ENABLE-NEXT: vfmulcph %xmm1, %xmm0, %xmm2 {%k1} {z}337; ENABLE-NEXT: vmovaps %xmm2, %xmm0338; ENABLE-NEXT: retq339;340; DISABLE-LABEL: fmulc_maskz:341; DISABLE: # %bb.0:342; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill343; DISABLE-NEXT: #APP344; DISABLE-NEXT: nop345; DISABLE-NEXT: #NO_APP346; DISABLE-NEXT: kmovb (%rdi), %k1347; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 {%k1} {z} # 16-byte Folded Reload348; DISABLE-NEXT: vmovaps %xmm2, %xmm0349; DISABLE-NEXT: retq350 351 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()352 %2 = load i8, ptr %mask353 %3 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %2)354 ret <4 x float> %3355}356 357define <4 x float> @fcmulc(<4 x float> %a0, <4 x float> %a1) {358; ENABLE-LABEL: fcmulc:359; ENABLE: # %bb.0:360; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill361; ENABLE-NEXT: #APP362; ENABLE-NEXT: nop363; ENABLE-NEXT: #NO_APP364; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload365; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2366; ENABLE-NEXT: vfcmulcph %xmm1, %xmm0, %xmm2367; ENABLE-NEXT: vmovaps %xmm2, %xmm0368; ENABLE-NEXT: retq369;370; DISABLE-LABEL: fcmulc:371; DISABLE: # %bb.0:372; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill373; DISABLE-NEXT: #APP374; DISABLE-NEXT: nop375; DISABLE-NEXT: #NO_APP376; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 # 16-byte Folded Reload377; DISABLE-NEXT: vmovaps %xmm2, %xmm0378; DISABLE-NEXT: retq379 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()380 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)381 ret <4 x float> %2382}383 384define <4 x float> @fcmulc_mem(<4 x float> %a0, ptr %p1) {385; ENABLE-LABEL: fcmulc_mem:386; ENABLE: # %bb.0:387; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill388; ENABLE-NEXT: #APP389; ENABLE-NEXT: nop390; ENABLE-NEXT: #NO_APP391; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload392; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1393; ENABLE-NEXT: vfcmulcph (%rdi), %xmm0, %xmm1394; ENABLE-NEXT: vmovaps %xmm1, %xmm0395; ENABLE-NEXT: retq396;397; DISABLE-LABEL: fcmulc_mem:398; DISABLE: # %bb.0:399; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill400; DISABLE-NEXT: #APP401; DISABLE-NEXT: nop402; DISABLE-NEXT: #NO_APP403; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload404; DISABLE-NEXT: vfcmulcph (%rdi), %xmm0, %xmm1405; DISABLE-NEXT: vmovaps %xmm1, %xmm0406; DISABLE-NEXT: retq407 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()408 %a1 = load <4 x float>, ptr %p1, align 64409 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)410 ret <4 x float> %2411}412 413define <4 x float> @fcmulc_broadcast(<4 x float> %a0, ptr %p1) {414; ENABLE-LABEL: fcmulc_broadcast:415; ENABLE: # %bb.0:416; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill417; ENABLE-NEXT: #APP418; ENABLE-NEXT: nop419; ENABLE-NEXT: #NO_APP420; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload421; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1422; ENABLE-NEXT: vfcmulcph (%rdi){1to4}, %xmm0, %xmm1423; ENABLE-NEXT: vmovaps %xmm1, %xmm0424; ENABLE-NEXT: retq425;426; DISABLE-LABEL: fcmulc_broadcast:427; DISABLE: # %bb.0:428; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill429; DISABLE-NEXT: #APP430; DISABLE-NEXT: nop431; DISABLE-NEXT: #NO_APP432; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload433; DISABLE-NEXT: vfcmulcph (%rdi){1to4}, %xmm0, %xmm1434; DISABLE-NEXT: vmovaps %xmm1, %xmm0435; DISABLE-NEXT: retq436 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()437 %v1 = load float, ptr %p1, align 4438 %t0 = insertelement <4 x float> undef, float %v1, i64 0439 %a1 = shufflevector <4 x float> %t0, <4 x float> undef, <4 x i32> zeroinitializer440 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1)441 ret <4 x float> %2442}443 444define <4 x float> @fcmulc_maskz(<4 x float> %a0, <4 x float> %a1, ptr %mask) {445; ENABLE-LABEL: fcmulc_maskz:446; ENABLE: # %bb.0:447; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill448; ENABLE-NEXT: #APP449; ENABLE-NEXT: nop450; ENABLE-NEXT: #NO_APP451; ENABLE-NEXT: kmovb (%rdi), %k1452; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload453; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2454; ENABLE-NEXT: vfcmulcph %xmm1, %xmm0, %xmm2 {%k1} {z}455; ENABLE-NEXT: vmovaps %xmm2, %xmm0456; ENABLE-NEXT: retq457;458; DISABLE-LABEL: fcmulc_maskz:459; DISABLE: # %bb.0:460; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill461; DISABLE-NEXT: #APP462; DISABLE-NEXT: nop463; DISABLE-NEXT: #NO_APP464; DISABLE-NEXT: kmovb (%rdi), %k1465; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 {%k1} {z} # 16-byte Folded Reload466; DISABLE-NEXT: vmovaps %xmm2, %xmm0467; DISABLE-NEXT: retq468 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()469 %2 = load i8, ptr %mask470 %3 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float> %a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %2)471 ret <4 x float> %3472}473 474define <8 x float> @fmulc_ymm(<8 x float> %a0, <8 x float> %a1) {475; ENABLE-LABEL: fmulc_ymm:476; ENABLE: # %bb.0:477; ENABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill478; ENABLE-NEXT: #APP479; ENABLE-NEXT: nop480; ENABLE-NEXT: #NO_APP481; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload482; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2483; ENABLE-NEXT: vfmulcph %ymm1, %ymm0, %ymm2484; ENABLE-NEXT: vmovaps %ymm2, %ymm0485; ENABLE-NEXT: retq486;487; DISABLE-LABEL: fmulc_ymm:488; DISABLE: # %bb.0:489; DISABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill490; DISABLE-NEXT: #APP491; DISABLE-NEXT: nop492; DISABLE-NEXT: #NO_APP493; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm2 # 32-byte Folded Reload494; DISABLE-NEXT: vmovaps %ymm2, %ymm0495; DISABLE-NEXT: retq496 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()497 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)498 ret <8 x float> %2499}500 501define <8 x float> @fmulc_ymm_mem(<8 x float> %a0, ptr %p1) {502; ENABLE-LABEL: fmulc_ymm_mem:503; ENABLE: # %bb.0:504; ENABLE-NEXT: #APP505; ENABLE-NEXT: nop506; ENABLE-NEXT: #NO_APP507; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1508; ENABLE-NEXT: vfmulcph (%rdi), %ymm0, %ymm1509; ENABLE-NEXT: vmovaps %ymm1, %ymm0510; ENABLE-NEXT: retq511;512; DISABLE-LABEL: fmulc_ymm_mem:513; DISABLE: # %bb.0:514; DISABLE-NEXT: #APP515; DISABLE-NEXT: nop516; DISABLE-NEXT: #NO_APP517; DISABLE-NEXT: vfmulcph (%rdi), %ymm0, %ymm1518; DISABLE-NEXT: vmovaps %ymm1, %ymm0519; DISABLE-NEXT: retq520 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()521 %a1 = load <8 x float>, ptr %p1, align 64522 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)523 ret <8 x float> %2524}525 526define <8 x float> @fmulc_ymm_broadcast(<8 x float> %a0, ptr %p1) {527; ENABLE-LABEL: fmulc_ymm_broadcast:528; ENABLE: # %bb.0:529; ENABLE-NEXT: #APP530; ENABLE-NEXT: nop531; ENABLE-NEXT: #NO_APP532; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1533; ENABLE-NEXT: vfmulcph (%rdi){1to8}, %ymm0, %ymm1534; ENABLE-NEXT: vmovaps %ymm1, %ymm0535; ENABLE-NEXT: retq536;537; DISABLE-LABEL: fmulc_ymm_broadcast:538; DISABLE: # %bb.0:539; DISABLE-NEXT: #APP540; DISABLE-NEXT: nop541; DISABLE-NEXT: #NO_APP542; DISABLE-NEXT: vfmulcph (%rdi){1to8}, %ymm0, %ymm1543; DISABLE-NEXT: vmovaps %ymm1, %ymm0544; DISABLE-NEXT: retq545 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()546 %v1 = load float, ptr %p1, align 4547 %t0 = insertelement <8 x float> undef, float %v1, i64 0548 %a1 = shufflevector <8 x float> %t0, <8 x float> undef, <8 x i32> zeroinitializer549 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)550 ret <8 x float> %2551}552 553define <8 x float> @fmulc_maskz_ymm(<8 x float> %a0, <8 x float> %a1, ptr %mask) {554; ENABLE-LABEL: fmulc_maskz_ymm:555; ENABLE: # %bb.0:556; ENABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill557; ENABLE-NEXT: #APP558; ENABLE-NEXT: nop559; ENABLE-NEXT: #NO_APP560; ENABLE-NEXT: kmovb (%rdi), %k1561; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload562; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2563; ENABLE-NEXT: vfmulcph %ymm1, %ymm0, %ymm2 {%k1} {z}564; ENABLE-NEXT: vmovaps %ymm2, %ymm0565; ENABLE-NEXT: retq566;567; DISABLE-LABEL: fmulc_maskz_ymm:568; DISABLE: # %bb.0:569; DISABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill570; DISABLE-NEXT: #APP571; DISABLE-NEXT: nop572; DISABLE-NEXT: #NO_APP573; DISABLE-NEXT: kmovb (%rdi), %k1574; DISABLE-NEXT: vfmulcph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm2 {%k1} {z} # 32-byte Folded Reload575; DISABLE-NEXT: vmovaps %ymm2, %ymm0576; DISABLE-NEXT: retq577 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()578 %2 = load i8, ptr %mask579 %3 = call <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> zeroinitializer, i8 %2)580 ret <8 x float> %3581}582 583define <8 x float> @fcmulc_ymm(<8 x float> %a0, <8 x float> %a1) {584; ENABLE-LABEL: fcmulc_ymm:585; ENABLE: # %bb.0:586; ENABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill587; ENABLE-NEXT: #APP588; ENABLE-NEXT: nop589; ENABLE-NEXT: #NO_APP590; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload591; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2592; ENABLE-NEXT: vfcmulcph %ymm1, %ymm0, %ymm2593; ENABLE-NEXT: vmovaps %ymm2, %ymm0594; ENABLE-NEXT: retq595;596; DISABLE-LABEL: fcmulc_ymm:597; DISABLE: # %bb.0:598; DISABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill599; DISABLE-NEXT: #APP600; DISABLE-NEXT: nop601; DISABLE-NEXT: #NO_APP602; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm2 # 32-byte Folded Reload603; DISABLE-NEXT: vmovaps %ymm2, %ymm0604; DISABLE-NEXT: retq605 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()606 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)607 ret <8 x float> %2608}609 610define <8 x float> @fcmulc_ymm_mem(<8 x float> %a0, ptr %p1) {611; ENABLE-LABEL: fcmulc_ymm_mem:612; ENABLE: # %bb.0:613; ENABLE-NEXT: #APP614; ENABLE-NEXT: nop615; ENABLE-NEXT: #NO_APP616; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1617; ENABLE-NEXT: vfcmulcph (%rdi), %ymm0, %ymm1618; ENABLE-NEXT: vmovaps %ymm1, %ymm0619; ENABLE-NEXT: retq620;621; DISABLE-LABEL: fcmulc_ymm_mem:622; DISABLE: # %bb.0:623; DISABLE-NEXT: #APP624; DISABLE-NEXT: nop625; DISABLE-NEXT: #NO_APP626; DISABLE-NEXT: vfcmulcph (%rdi), %ymm0, %ymm1627; DISABLE-NEXT: vmovaps %ymm1, %ymm0628; DISABLE-NEXT: retq629 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()630 %a1 = load <8 x float>, ptr %p1, align 64631 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)632 ret <8 x float> %2633}634 635define <8 x float> @fcmulc_ymm_broadcast(<8 x float> %a0, ptr %p1) {636; ENABLE-LABEL: fcmulc_ymm_broadcast:637; ENABLE: # %bb.0:638; ENABLE-NEXT: #APP639; ENABLE-NEXT: nop640; ENABLE-NEXT: #NO_APP641; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1642; ENABLE-NEXT: vfcmulcph (%rdi){1to8}, %ymm0, %ymm1643; ENABLE-NEXT: vmovaps %ymm1, %ymm0644; ENABLE-NEXT: retq645;646; DISABLE-LABEL: fcmulc_ymm_broadcast:647; DISABLE: # %bb.0:648; DISABLE-NEXT: #APP649; DISABLE-NEXT: nop650; DISABLE-NEXT: #NO_APP651; DISABLE-NEXT: vfcmulcph (%rdi){1to8}, %ymm0, %ymm1652; DISABLE-NEXT: vmovaps %ymm1, %ymm0653; DISABLE-NEXT: retq654 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()655 %v1 = load float, ptr %p1, align 4656 %t0 = insertelement <8 x float> undef, float %v1, i64 0657 %a1 = shufflevector <8 x float> %t0, <8 x float> undef, <8 x i32> zeroinitializer658 %2 = call <8 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> undef, i8 -1)659 ret <8 x float> %2660}661 662define <8 x float> @fcmulc_maskz_ymm(<8 x float> %a0, <8 x float> %a1, ptr %mask) {663; ENABLE-LABEL: fcmulc_maskz_ymm:664; ENABLE: # %bb.0:665; ENABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill666; ENABLE-NEXT: #APP667; ENABLE-NEXT: nop668; ENABLE-NEXT: #NO_APP669; ENABLE-NEXT: kmovb (%rdi), %k1670; ENABLE-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload671; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2672; ENABLE-NEXT: vfcmulcph %ymm1, %ymm0, %ymm2 {%k1} {z}673; ENABLE-NEXT: vmovaps %ymm2, %ymm0674; ENABLE-NEXT: retq675;676; DISABLE-LABEL: fcmulc_maskz_ymm:677; DISABLE: # %bb.0:678; DISABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill679; DISABLE-NEXT: #APP680; DISABLE-NEXT: nop681; DISABLE-NEXT: #NO_APP682; DISABLE-NEXT: kmovb (%rdi), %k1683; DISABLE-NEXT: vfcmulcph {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm2 {%k1} {z} # 32-byte Folded Reload684; DISABLE-NEXT: vmovaps %ymm2, %ymm0685; DISABLE-NEXT: retq686 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()687 %2 = load i8, ptr %mask688 %3 = call <8 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.256(<8 x float> %a0, <8 x float> %a1, <8 x float> zeroinitializer, i8 %2)689 ret <8 x float> %3690}691 692define <4 x float> @fmulcsh(<4 x float> %a0, <4 x float> %a1) {693; ENABLE-LABEL: fmulcsh:694; ENABLE: # %bb.0:695; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill696; ENABLE-NEXT: #APP697; ENABLE-NEXT: nop698; ENABLE-NEXT: #NO_APP699; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload700; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2701; ENABLE-NEXT: vfmulcsh %xmm1, %xmm0, %xmm2702; ENABLE-NEXT: vmovaps %xmm2, %xmm0703; ENABLE-NEXT: retq704;705; DISABLE-LABEL: fmulcsh:706; DISABLE: # %bb.0:707; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill708; DISABLE-NEXT: #APP709; DISABLE-NEXT: nop710; DISABLE-NEXT: #NO_APP711; DISABLE-NEXT: vfmulcsh {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 # 16-byte Folded Reload712; DISABLE-NEXT: vmovaps %xmm2, %xmm0713; DISABLE-NEXT: retq714 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()715 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1, i32 4)716 ret <4 x float> %2717}718 719define <4 x float> @fmulcsh_mem(<4 x float> %a0, ptr %p1) {720; ENABLE-LABEL: fmulcsh_mem:721; ENABLE: # %bb.0:722; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill723; ENABLE-NEXT: #APP724; ENABLE-NEXT: nop725; ENABLE-NEXT: #NO_APP726; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload727; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1728; ENABLE-NEXT: vfmulcsh (%rdi), %xmm0, %xmm1729; ENABLE-NEXT: vmovaps %xmm1, %xmm0730; ENABLE-NEXT: retq731;732; DISABLE-LABEL: fmulcsh_mem:733; DISABLE: # %bb.0:734; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill735; DISABLE-NEXT: #APP736; DISABLE-NEXT: nop737; DISABLE-NEXT: #NO_APP738; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload739; DISABLE-NEXT: vfmulcsh (%rdi), %xmm0, %xmm1740; DISABLE-NEXT: vmovaps %xmm1, %xmm0741; DISABLE-NEXT: retq742 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()743 %a1 = load <4 x float>, ptr %p1, align 64744 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1, i32 4)745 ret <4 x float> %2746}747 748define <4 x float> @fmulcsh_maskz(<4 x float> %a0, <4 x float> %a1, ptr %mask) {749; ENABLE-LABEL: fmulcsh_maskz:750; ENABLE: # %bb.0:751; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill752; ENABLE-NEXT: #APP753; ENABLE-NEXT: nop754; ENABLE-NEXT: #NO_APP755; ENABLE-NEXT: kmovb (%rdi), %k1756; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload757; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2758; ENABLE-NEXT: vfmulcsh %xmm1, %xmm0, %xmm2 {%k1} {z}759; ENABLE-NEXT: vmovaps %xmm2, %xmm0760; ENABLE-NEXT: retq761;762; DISABLE-LABEL: fmulcsh_maskz:763; DISABLE: # %bb.0:764; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill765; DISABLE-NEXT: #APP766; DISABLE-NEXT: nop767; DISABLE-NEXT: #NO_APP768; DISABLE-NEXT: kmovb (%rdi), %k1769; DISABLE-NEXT: vfmulcsh {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 {%k1} {z} # 16-byte Folded Reload770; DISABLE-NEXT: vmovaps %xmm2, %xmm0771; DISABLE-NEXT: retq772 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()773 %2 = load i8, ptr %mask774 %3 = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %2, i32 4)775 ret <4 x float> %3776}777 778define <4 x float> @fcmulcsh(<4 x float> %a0, <4 x float> %a1) {779; ENABLE-LABEL: fcmulcsh:780; ENABLE: # %bb.0:781; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill782; ENABLE-NEXT: #APP783; ENABLE-NEXT: nop784; ENABLE-NEXT: #NO_APP785; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload786; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2787; ENABLE-NEXT: vfcmulcsh %xmm1, %xmm0, %xmm2788; ENABLE-NEXT: vmovaps %xmm2, %xmm0789; ENABLE-NEXT: retq790;791; DISABLE-LABEL: fcmulcsh:792; DISABLE: # %bb.0:793; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill794; DISABLE-NEXT: #APP795; DISABLE-NEXT: nop796; DISABLE-NEXT: #NO_APP797; DISABLE-NEXT: vfcmulcsh {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 # 16-byte Folded Reload798; DISABLE-NEXT: vmovaps %xmm2, %xmm0799; DISABLE-NEXT: retq800 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()801 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1, i32 4)802 ret <4 x float> %2803}804 805define <4 x float> @fcmulcsh_mem(<4 x float> %a0, ptr %p1) {806; ENABLE-LABEL: fcmulcsh_mem:807; ENABLE: # %bb.0:808; ENABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill809; ENABLE-NEXT: #APP810; ENABLE-NEXT: nop811; ENABLE-NEXT: #NO_APP812; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload813; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1814; ENABLE-NEXT: vfcmulcsh (%rdi), %xmm0, %xmm1815; ENABLE-NEXT: vmovaps %xmm1, %xmm0816; ENABLE-NEXT: retq817;818; DISABLE-LABEL: fcmulcsh_mem:819; DISABLE: # %bb.0:820; DISABLE-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill821; DISABLE-NEXT: #APP822; DISABLE-NEXT: nop823; DISABLE-NEXT: #NO_APP824; DISABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload825; DISABLE-NEXT: vfcmulcsh (%rdi), %xmm0, %xmm1826; DISABLE-NEXT: vmovaps %xmm1, %xmm0827; DISABLE-NEXT: retq828 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()829 %a1 = load <4 x float>, ptr %p1, align 64830 %2 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> undef, i8 -1, i32 4)831 ret <4 x float> %2832}833 834define <4 x float> @fcmulcsh_maskz(<4 x float> %a0, <4 x float> %a1, ptr %mask) {835; ENABLE-LABEL: fcmulcsh_maskz:836; ENABLE: # %bb.0:837; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill838; ENABLE-NEXT: #APP839; ENABLE-NEXT: nop840; ENABLE-NEXT: #NO_APP841; ENABLE-NEXT: kmovb (%rdi), %k1842; ENABLE-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload843; ENABLE-NEXT: vxorps %xmm2, %xmm2, %xmm2844; ENABLE-NEXT: vfcmulcsh %xmm1, %xmm0, %xmm2 {%k1} {z}845; ENABLE-NEXT: vmovaps %xmm2, %xmm0846; ENABLE-NEXT: retq847;848; DISABLE-LABEL: fcmulcsh_maskz:849; DISABLE: # %bb.0:850; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill851; DISABLE-NEXT: #APP852; DISABLE-NEXT: nop853; DISABLE-NEXT: #NO_APP854; DISABLE-NEXT: kmovb (%rdi), %k1855; DISABLE-NEXT: vfcmulcsh {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm2 {%k1} {z} # 16-byte Folded Reload856; DISABLE-NEXT: vmovaps %xmm2, %xmm0857; DISABLE-NEXT: retq858 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()859 %2 = load i8, ptr %mask860 %3 = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %a0, <4 x float> %a1, <4 x float> zeroinitializer, i8 %2, i32 4)861 ret <4 x float> %3862}863 864declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)865declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)866declare <16 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)867declare <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)868declare <8 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)869declare <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)870declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)871declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)872 873