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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX3 4declare { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>)5declare { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32>, <4 x i32>)6 7define <4 x i32> @umul_v4i32_0(<4 x i32> %a, <4 x i32> %b) nounwind {8; AVX-LABEL: umul_v4i32_0:9; AVX: # %bb.0:10; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm011; AVX-NEXT: retq12 %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)13 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 014 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 115 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y16 ret <4 x i32> %u17}18 19define <4 x i32> @umul_v4i32_1(<4 x i32> %a, <4 x i32> %b) nounwind {20; AVX-LABEL: umul_v4i32_1:21; AVX: # %bb.0:22; AVX-NEXT: retq23 %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)24 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 025 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 126 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y27 ret <4 x i32> %u28}29 30define <4 x i32> @umul_v4i32_2(<4 x i32> %a, <4 x i32> %b) nounwind {31; AVX-LABEL: umul_v4i32_2:32; AVX: # %bb.0:33; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm234; AVX-NEXT: vpmaxud %xmm0, %xmm2, %xmm035; AVX-NEXT: vpcmpeqd %xmm0, %xmm2, %xmm036; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm037; AVX-NEXT: retq38 %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)39 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 040 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 141 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y42 ret <4 x i32> %u43}44 45define <4 x i32> @umul_v4i32_8(<4 x i32> %a, <4 x i32> %b) nounwind {46; AVX-LABEL: umul_v4i32_8:47; AVX: # %bb.0:48; AVX-NEXT: vpslld $3, %xmm0, %xmm249; AVX-NEXT: vpsrld $3, %xmm2, %xmm350; AVX-NEXT: vpcmpeqd %xmm0, %xmm3, %xmm051; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm052; AVX-NEXT: retq53 %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)54 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 055 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 156 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y57 ret <4 x i32> %u58}59 60define <4 x i32> @umul_v4i32_2pow31(<4 x i32> %a, <4 x i32> %b) nounwind {61; AVX-LABEL: umul_v4i32_2pow31:62; AVX: # %bb.0:63; AVX-NEXT: vpslld $31, %xmm0, %xmm264; AVX-NEXT: vpsrld $31, %xmm2, %xmm365; AVX-NEXT: vpcmpeqd %xmm0, %xmm3, %xmm066; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm067; AVX-NEXT: retq68 %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>)69 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 070 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 171 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y72 ret <4 x i32> %u73}74 75define <4 x i32> @smul_v4i32_0(<4 x i32> %a, <4 x i32> %b) nounwind {76; AVX-LABEL: smul_v4i32_0:77; AVX: # %bb.0:78; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm079; AVX-NEXT: retq80 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)81 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 082 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 183 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y84 ret <4 x i32> %u85}86 87define <4 x i32> @smul_v4i32_1(<4 x i32> %a, <4 x i32> %b) nounwind {88; AVX-LABEL: smul_v4i32_1:89; AVX: # %bb.0:90; AVX-NEXT: retq91 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)92 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 093 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 194 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y95 ret <4 x i32> %u96}97 98define <4 x i32> @smul_v4i32_2(<4 x i32> %a, <4 x i32> %b) nounwind {99; AVX-LABEL: smul_v4i32_2:100; AVX: # %bb.0:101; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm2102; AVX-NEXT: vpcmpgtd %xmm2, %xmm0, %xmm3103; AVX-NEXT: vpxor %xmm3, %xmm0, %xmm0104; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0105; AVX-NEXT: retq106 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)107 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0108 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1109 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y110 ret <4 x i32> %u111}112 113define <4 x i32> @smul_v4i32_8(<4 x i32> %a, <4 x i32> %b) nounwind {114; AVX-LABEL: smul_v4i32_8:115; AVX: # %bb.0:116; AVX-NEXT: vpslld $3, %xmm0, %xmm2117; AVX-NEXT: vpsrad $3, %xmm2, %xmm3118; AVX-NEXT: vpcmpeqd %xmm0, %xmm3, %xmm0119; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0120; AVX-NEXT: retq121 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)122 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0123 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1124 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y125 ret <4 x i32> %u126}127 128define <4 x i32> @smul_v4i32_2pow31(<4 x i32> %a, <4 x i32> %b) nounwind {129; AVX-LABEL: smul_v4i32_2pow31:130; AVX: # %bb.0:131; AVX-NEXT: vpslld $31, %xmm0, %xmm2132; AVX-NEXT: vpsrld $31, %xmm2, %xmm3133; AVX-NEXT: vpcmpeqd %xmm0, %xmm3, %xmm0134; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0135; AVX-NEXT: retq136 %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>)137 %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0138 %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1139 %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y140 ret <4 x i32> %u141}142