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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE424; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX15; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX26 7; PR63998 9define <2 x i32> @_mul2xi32a(<2 x i32>, <2 x i32>) {10; SSE2-LABEL: _mul2xi32a:11; SSE2: # %bb.0:12; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]13; SSE2-NEXT: pmuludq %xmm1, %xmm014; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]15; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]16; SSE2-NEXT: pmuludq %xmm2, %xmm117; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]18; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]19; SSE2-NEXT: retq20;21; SSE42-LABEL: _mul2xi32a:22; SSE42: # %bb.0:23; SSE42-NEXT: pmulld %xmm1, %xmm024; SSE42-NEXT: retq25;26; AVX-LABEL: _mul2xi32a:27; AVX: # %bb.0:28; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm029; AVX-NEXT: retq30 %r = mul <2 x i32> %0, %131 ret <2 x i32> %r32}33 34define <2 x i32> @_mul2xi32b(<2 x i32>, <2 x i32>) {35; SSE-LABEL: _mul2xi32b:36; SSE: # %bb.0:37; SSE-NEXT: pmuludq %xmm1, %xmm038; SSE-NEXT: retq39;40; AVX-LABEL: _mul2xi32b:41; AVX: # %bb.0:42; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm043; AVX-NEXT: retq44 %factor0 = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>45 %factor1 = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>46 %product64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %factor0, <4 x i32> %factor1) readnone47 %product = bitcast <2 x i64> %product64 to <4 x i32>48 %r = shufflevector <4 x i32> %product, <4 x i32> undef, <2 x i32> <i32 0, i32 4>49 ret <2 x i32> %r50}51 52define <4 x i32> @_mul4xi32a(<4 x i32>, <4 x i32>) {53; SSE2-LABEL: _mul4xi32a:54; SSE2: # %bb.0:55; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]56; SSE2-NEXT: pmuludq %xmm1, %xmm057; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]58; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]59; SSE2-NEXT: pmuludq %xmm2, %xmm160; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]61; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]62; SSE2-NEXT: retq63;64; SSE42-LABEL: _mul4xi32a:65; SSE42: # %bb.0:66; SSE42-NEXT: pmulld %xmm1, %xmm067; SSE42-NEXT: retq68;69; AVX-LABEL: _mul4xi32a:70; AVX: # %bb.0:71; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm072; AVX-NEXT: retq73 %r = mul <4 x i32> %0, %174 ret <4 x i32> %r75}76 77define <4 x i32> @_mul4xi32b(<4 x i32>, <4 x i32>) {78; SSE2-LABEL: _mul4xi32b:79; SSE2: # %bb.0:80; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]81; SSE2-NEXT: pmuludq %xmm1, %xmm082; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]83; SSE2-NEXT: pmuludq %xmm2, %xmm184; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]85; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]86; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]87; SSE2-NEXT: retq88;89; SSE42-LABEL: _mul4xi32b:90; SSE42: # %bb.0:91; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]92; SSE42-NEXT: pmuludq %xmm1, %xmm093; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]94; SSE42-NEXT: pmuludq %xmm2, %xmm195; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]96; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]97; SSE42-NEXT: retq98;99; AVX1-LABEL: _mul4xi32b:100; AVX1: # %bb.0:101; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2102; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]103; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]104; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0105; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]106; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]107; AVX1-NEXT: retq108;109; AVX2-LABEL: _mul4xi32b:110; AVX2: # %bb.0:111; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2112; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]113; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]114; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0115; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]116; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]117; AVX2-NEXT: retq118 %even0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>119 %even1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>120 %evenMul64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %even0, <4 x i32> %even1) readnone121 %evenMul = bitcast <2 x i64> %evenMul64 to <4 x i32>122 %odd0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>123 %odd1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>124 %oddMul64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %odd0, <4 x i32> %odd1) readnone125 %oddMul = bitcast <2 x i64> %oddMul64 to <4 x i32>126 %r = shufflevector <4 x i32> %evenMul, <4 x i32> %oddMul, <4 x i32> <i32 0, i32 4, i32 2, i32 6>127 ret <4 x i32> %r128}129 130; the following extractelement's and insertelement's131; are just an unrolled 'zext' on a vector132; %ext0 = zext <4 x i32> %0 to <4 x i64>133; %ext1 = zext <4 x i32> %1 to <4 x i64>134define <4 x i64> @_mul4xi32toi64a(<4 x i32>, <4 x i32>) {135; SSE2-LABEL: _mul4xi32toi64a:136; SSE2: # %bb.0:137; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]138; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,1,3,3]139; SSE2-NEXT: pmuludq %xmm3, %xmm2140; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,1,3]141; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]142; SSE2-NEXT: pmuludq %xmm1, %xmm0143; SSE2-NEXT: movdqa %xmm2, %xmm1144; SSE2-NEXT: retq145;146; SSE42-LABEL: _mul4xi32toi64a:147; SSE42: # %bb.0:148; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]149; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,1,3,3]150; SSE42-NEXT: pmuludq %xmm3, %xmm2151; SSE42-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero152; SSE42-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero153; SSE42-NEXT: pmuludq %xmm1, %xmm0154; SSE42-NEXT: movdqa %xmm2, %xmm1155; SSE42-NEXT: retq156;157; AVX1-LABEL: _mul4xi32toi64a:158; AVX1: # %bb.0:159; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,2,3,3]160; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[2,2,3,3]161; AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2162; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero163; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero164; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0165; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0166; AVX1-NEXT: retq167;168; AVX2-LABEL: _mul4xi32toi64a:169; AVX2: # %bb.0:170; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero171; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero172; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0173; AVX2-NEXT: retq174 %f00 = extractelement <4 x i32> %0, i32 0175 %f01 = extractelement <4 x i32> %0, i32 1176 %f02 = extractelement <4 x i32> %0, i32 2177 %f03 = extractelement <4 x i32> %0, i32 3178 %f10 = extractelement <4 x i32> %1, i32 0179 %f11 = extractelement <4 x i32> %1, i32 1180 %f12 = extractelement <4 x i32> %1, i32 2181 %f13 = extractelement <4 x i32> %1, i32 3182 %ext00 = zext i32 %f00 to i64183 %ext01 = zext i32 %f01 to i64184 %ext02 = zext i32 %f02 to i64185 %ext03 = zext i32 %f03 to i64186 %ext10 = zext i32 %f10 to i64187 %ext11 = zext i32 %f11 to i64188 %ext12 = zext i32 %f12 to i64189 %ext13 = zext i32 %f13 to i64190 %extv00 = insertelement <4 x i64> undef, i64 %ext00, i32 0191 %extv01 = insertelement <4 x i64> %extv00, i64 %ext01, i32 1192 %extv02 = insertelement <4 x i64> %extv01, i64 %ext02, i32 2193 %extv03 = insertelement <4 x i64> %extv02, i64 %ext03, i32 3194 %extv10 = insertelement <4 x i64> undef, i64 %ext10, i32 0195 %extv11 = insertelement <4 x i64> %extv10, i64 %ext11, i32 1196 %extv12 = insertelement <4 x i64> %extv11, i64 %ext12, i32 2197 %extv13 = insertelement <4 x i64> %extv12, i64 %ext13, i32 3198 %r = mul <4 x i64> %extv03, %extv13199 ret <4 x i64> %r200}201 202; very similar to mul4xi32 above203; there is no bitcast and the final shuffle is a little different204define <4 x i64> @_mul4xi32toi64b(<4 x i32>, <4 x i32>) {205; SSE-LABEL: _mul4xi32toi64b:206; SSE: # %bb.0:207; SSE-NEXT: movdqa %xmm0, %xmm2208; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]209; SSE-NEXT: pmuludq %xmm1, %xmm2210; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]211; SSE-NEXT: pmuludq %xmm0, %xmm1212; SSE-NEXT: movdqa %xmm2, %xmm0213; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]214; SSE-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]215; SSE-NEXT: movdqa %xmm2, %xmm1216; SSE-NEXT: retq217;218; AVX1-LABEL: _mul4xi32toi64b:219; AVX1: # %bb.0:220; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2221; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]222; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]223; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0224; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm2[1],xmm0[1]225; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]226; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0227; AVX1-NEXT: retq228;229; AVX2-LABEL: _mul4xi32toi64b:230; AVX2: # %bb.0:231; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2232; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]233; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]234; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0235; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm2[1],xmm0[1]236; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]237; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0238; AVX2-NEXT: retq239 %even0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>240 %even1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>241 %evenMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %even0, <4 x i32> %even1) readnone242 %odd0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>243 %odd1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>244 %oddMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %odd0, <4 x i32> %odd1) readnone245 %r = shufflevector <2 x i64> %evenMul, <2 x i64> %oddMul, <4 x i32> <i32 0, i32 2, i32 1, i32 3>246 ret <4 x i64> %r247}248 249; Here we do not split into even and odd indexed elements250; but into the lower and the upper half of the factor vectors.251; This makes the initial shuffle more complicated,252; but the final shuffle is a no-op.253define <4 x i64> @_mul4xi32toi64c(<4 x i32>, <4 x i32>) {254; SSE2-LABEL: _mul4xi32toi64c:255; SSE2: # %bb.0:256; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,1,1,3]257; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]258; SSE2-NEXT: pmuludq %xmm3, %xmm2259; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,3,3]260; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]261; SSE2-NEXT: pmuludq %xmm0, %xmm1262; SSE2-NEXT: movdqa %xmm2, %xmm0263; SSE2-NEXT: retq264;265; SSE42-LABEL: _mul4xi32toi64c:266; SSE42: # %bb.0:267; SSE42-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero268; SSE42-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero269; SSE42-NEXT: pmuludq %xmm3, %xmm2270; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]271; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]272; SSE42-NEXT: pmuludq %xmm0, %xmm1273; SSE42-NEXT: movdqa %xmm2, %xmm0274; SSE42-NEXT: retq275;276; AVX1-LABEL: _mul4xi32toi64c:277; AVX1: # %bb.0:278; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero279; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero280; AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2281; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]282; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]283; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0284; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0285; AVX1-NEXT: retq286;287; AVX2-LABEL: _mul4xi32toi64c:288; AVX2: # %bb.0:289; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero290; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero291; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0292; AVX2-NEXT: retq293 %lower0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>294 %lower1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>295 %lowerMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %lower0, <4 x i32> %lower1) readnone296 %upper0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 3, i32 undef>297 %upper1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 3, i32 undef>298 %upperMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %upper0, <4 x i32> %upper1) readnone299 %r = shufflevector <2 x i64> %lowerMul, <2 x i64> %upperMul, <4 x i32> <i32 0, i32 1, i32 2, i32 3>300 ret <4 x i64> %r301}302 303; If we know, that the most significant half of i64 elements are zero,304; then multiplication can be simplified drastically.305; In the following example I assert a zero upper half306; by 'trunc' followed by 'zext'.307;308; the following extractelement's and insertelement's309; are just an unrolled 'trunc' plus 'zext' on a vector310; %trunc0 = trunc <2 x i64> %0 to <2 x i32>311; %trunc1 = trunc <2 x i64> %1 to <2 x i32>312; %ext0 = zext <2 x i32> %0 to <2 x i64>313; %ext1 = zext <2 x i32> %1 to <2 x i64>314define <2 x i64> @_mul2xi64toi64a(<2 x i64>, <2 x i64>) {315; SSE-LABEL: _mul2xi64toi64a:316; SSE: # %bb.0:317; SSE-NEXT: pmuludq %xmm1, %xmm0318; SSE-NEXT: retq319;320; AVX-LABEL: _mul2xi64toi64a:321; AVX: # %bb.0:322; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0323; AVX-NEXT: retq324 %f00 = extractelement <2 x i64> %0, i32 0325 %f01 = extractelement <2 x i64> %0, i32 1326 %f10 = extractelement <2 x i64> %1, i32 0327 %f11 = extractelement <2 x i64> %1, i32 1328 %trunc00 = trunc i64 %f00 to i32329 %trunc01 = trunc i64 %f01 to i32330 %ext00 = zext i32 %trunc00 to i64331 %ext01 = zext i32 %trunc01 to i64332 %trunc10 = trunc i64 %f10 to i32333 %trunc11 = trunc i64 %f11 to i32334 %ext10 = zext i32 %trunc10 to i64335 %ext11 = zext i32 %trunc11 to i64336 %extv00 = insertelement <2 x i64> undef, i64 %ext00, i32 0337 %extv01 = insertelement <2 x i64> %extv00, i64 %ext01, i32 1338 %extv10 = insertelement <2 x i64> undef, i64 %ext10, i32 0339 %extv11 = insertelement <2 x i64> %extv10, i64 %ext11, i32 1340 %r = mul <2 x i64> %extv01, %extv11341 ret <2 x i64> %r342}343 344define <2 x i64> @_mul2xi64toi64b(<2 x i64>, <2 x i64>) {345; SSE-LABEL: _mul2xi64toi64b:346; SSE: # %bb.0:347; SSE-NEXT: pmuludq %xmm1, %xmm0348; SSE-NEXT: retq349;350; AVX-LABEL: _mul2xi64toi64b:351; AVX: # %bb.0:352; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0353; AVX-NEXT: retq354 %f0 = bitcast <2 x i64> %0 to <4 x i32>355 %f1 = bitcast <2 x i64> %1 to <4 x i32>356 %r = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %f0, <4 x i32> %f1) readnone357 ret <2 x i64> %r358}359 360declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone361