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1; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE22; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX3; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx,+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F4; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512VL5 6; While we don't support varargs with fastcall, we do support forwarding.7 8@asdf = internal constant [4 x i8] c"asdf"9 10declare void @puts(ptr)11 12define i32 @call_fast_thunk() {13 %r = call x86_fastcallcc i32 (...) @fast_thunk(i32 inreg 1, i32 inreg 2, i32 3)14 ret i32 %r15}16 17define x86_fastcallcc i32 @fast_thunk(...) {18 call void @puts(ptr @asdf)19 %r = musttail call x86_fastcallcc i32 (...) @fast_target (...)20 ret i32 %r21}22 23; Check that we spill and fill around the call to puts.24 25; CHECK-LABEL: @fast_thunk@0:26; CHECK-DAG: movl %ecx, {{.*}}27; CHECK-DAG: movl %edx, {{.*}}28; CHECK: calll _puts29; CHECK-DAG: movl {{.*}}, %ecx30; CHECK-DAG: movl {{.*}}, %edx31; CHECK: jmp @fast_target@1232 33define x86_fastcallcc i32 @fast_target(i32 inreg %a, i32 inreg %b, i32 %c) {34 %a0 = add i32 %a, %b35 %a1 = add i32 %a0, %c36 ret i32 %a137}38 39; Repeat the test for vectorcall, which has XMM registers.40 41define i32 @call_vector_thunk() {42 %r = call x86_vectorcallcc i32 (...) @vector_thunk(i32 inreg 1, i32 inreg 2, i32 3)43 ret i32 %r44}45 46define x86_vectorcallcc i32 @vector_thunk(...) {47 call void @puts(ptr @asdf)48 %r = musttail call x86_vectorcallcc i32 (...) @vector_target (...)49 ret i32 %r50}51 52; Check that we spill and fill SSE registers around the call to puts.53 54; CHECK-LABEL: vector_thunk@@0:55; CHECK-DAG: movl %ecx, {{.*}}56; CHECK-DAG: movl %edx, {{.*}}57 58; SSE2-DAG: movups %xmm0, {{.*}}59; SSE2-DAG: movups %xmm1, {{.*}}60; SSE2-DAG: movups %xmm2, {{.*}}61; SSE2-DAG: movups %xmm3, {{.*}}62; SSE2-DAG: movups %xmm4, {{.*}}63; SSE2-DAG: movups %xmm5, {{.*}}64 65; AVX-DAG: vmovups %ymm0, {{.*}}66; AVX-DAG: vmovups %ymm1, {{.*}}67; AVX-DAG: vmovups %ymm2, {{.*}}68; AVX-DAG: vmovups %ymm3, {{.*}}69; AVX-DAG: vmovups %ymm4, {{.*}}70; AVX-DAG: vmovups %ymm5, {{.*}}71 72; AVX512-DAG: vmovups %zmm0, {{.*}}73; AVX512-DAG: vmovups %zmm1, {{.*}}74; AVX512-DAG: vmovups %zmm2, {{.*}}75; AVX512-DAG: vmovups %zmm3, {{.*}}76; AVX512-DAG: vmovups %zmm4, {{.*}}77; AVX512-DAG: vmovups %zmm5, {{.*}}78 79; CHECK: calll _puts80 81; SSE2-DAG: movups {{.*}}, %xmm082; SSE2-DAG: movups {{.*}}, %xmm183; SSE2-DAG: movups {{.*}}, %xmm284; SSE2-DAG: movups {{.*}}, %xmm385; SSE2-DAG: movups {{.*}}, %xmm486; SSE2-DAG: movups {{.*}}, %xmm587 88; AVX-DAG: vmovups {{.*}}, %ymm089; AVX-DAG: vmovups {{.*}}, %ymm190; AVX-DAG: vmovups {{.*}}, %ymm291; AVX-DAG: vmovups {{.*}}, %ymm392; AVX-DAG: vmovups {{.*}}, %ymm493; AVX-DAG: vmovups {{.*}}, %ymm594 95; AVX512-DAG: vmovups {{.*}}, %zmm096; AVX512-DAG: vmovups {{.*}}, %zmm197; AVX512-DAG: vmovups {{.*}}, %zmm298; AVX512-DAG: vmovups {{.*}}, %zmm399; AVX512-DAG: vmovups {{.*}}, %zmm4100; AVX512-DAG: vmovups {{.*}}, %zmm5101 102; CHECK-DAG: movl {{.*}}, %ecx103; CHECK-DAG: movl {{.*}}, %edx104; CHECK: jmp vector_target@@12105 106define x86_vectorcallcc i32 @vector_target(i32 inreg %a, i32 inreg %b, i32 %c) {107 %a0 = add i32 %a, %b108 %a1 = add i32 %a0, %c109 ret i32 %a1110}111 112; Repeat the test for vectorcall, which has XMM registers.113 114define i32 @call_vector_thunk_prefer256() "min-legal-vector-width"="256" "prefer-vector-width"="256" {115 %r = call x86_vectorcallcc i32 (...) @vector_thunk_prefer256(i32 inreg 1, i32 inreg 2, i32 3)116 ret i32 %r117}118 119define x86_vectorcallcc i32 @vector_thunk_prefer256(...) "min-legal-vector-width"="256" "prefer-vector-width"="256" {120 call void @puts(ptr @asdf)121 %r = musttail call x86_vectorcallcc i32 (...) @vector_target_prefer256 (...)122 ret i32 %r123}124 125; Check that we spill and fill SSE registers around the call to puts.126 127; CHECK-LABEL: vector_thunk_prefer256@@0:128; CHECK-DAG: movl %ecx, {{.*}}129; CHECK-DAG: movl %edx, {{.*}}130 131; SSE2-DAG: movups %xmm0, {{.*}}132; SSE2-DAG: movups %xmm1, {{.*}}133; SSE2-DAG: movups %xmm2, {{.*}}134; SSE2-DAG: movups %xmm3, {{.*}}135; SSE2-DAG: movups %xmm4, {{.*}}136; SSE2-DAG: movups %xmm5, {{.*}}137 138; AVX-DAG: vmovups %ymm0, {{.*}}139; AVX-DAG: vmovups %ymm1, {{.*}}140; AVX-DAG: vmovups %ymm2, {{.*}}141; AVX-DAG: vmovups %ymm3, {{.*}}142; AVX-DAG: vmovups %ymm4, {{.*}}143; AVX-DAG: vmovups %ymm5, {{.*}}144 145; AVX512F-DAG: vmovups %zmm0, {{.*}}146; AVX512F-DAG: vmovups %zmm1, {{.*}}147; AVX512F-DAG: vmovups %zmm2, {{.*}}148; AVX512F-DAG: vmovups %zmm3, {{.*}}149; AVX512F-DAG: vmovups %zmm4, {{.*}}150; AVX512F-DAG: vmovups %zmm5, {{.*}}151 152; AVX512VL-DAG: vmovups %ymm0, {{.*}}153; AVX512VL-DAG: vmovups %ymm1, {{.*}}154; AVX512VL-DAG: vmovups %ymm2, {{.*}}155; AVX512VL-DAG: vmovups %ymm3, {{.*}}156; AVX512VL-DAG: vmovups %ymm4, {{.*}}157; AVX512VL-DAG: vmovups %ymm5, {{.*}}158 159; CHECK: calll _puts160 161; SSE2-DAG: movups {{.*}}, %xmm0162; SSE2-DAG: movups {{.*}}, %xmm1163; SSE2-DAG: movups {{.*}}, %xmm2164; SSE2-DAG: movups {{.*}}, %xmm3165; SSE2-DAG: movups {{.*}}, %xmm4166; SSE2-DAG: movups {{.*}}, %xmm5167 168; AVX-DAG: vmovups {{.*}}, %ymm0169; AVX-DAG: vmovups {{.*}}, %ymm1170; AVX-DAG: vmovups {{.*}}, %ymm2171; AVX-DAG: vmovups {{.*}}, %ymm3172; AVX-DAG: vmovups {{.*}}, %ymm4173; AVX-DAG: vmovups {{.*}}, %ymm5174 175; AVX512F-DAG: vmovups {{.*}}, %zmm0176; AVX512F-DAG: vmovups {{.*}}, %zmm1177; AVX512F-DAG: vmovups {{.*}}, %zmm2178; AVX512F-DAG: vmovups {{.*}}, %zmm3179; AVX512F-DAG: vmovups {{.*}}, %zmm4180; AVX512F-DAG: vmovups {{.*}}, %zmm5181 182; AVX512VL-DAG: vmovups {{.*}}, %ymm0183; AVX512VL-DAG: vmovups {{.*}}, %ymm1184; AVX512VL-DAG: vmovups {{.*}}, %ymm2185; AVX512VL-DAG: vmovups {{.*}}, %ymm3186; AVX512VL-DAG: vmovups {{.*}}, %ymm4187; AVX512VL-DAG: vmovups {{.*}}, %ymm5188 189; CHECK-DAG: movl {{.*}}, %ecx190; CHECK-DAG: movl {{.*}}, %edx191; CHECK: jmp vector_target_prefer256@@12192 193define x86_vectorcallcc i32 @vector_target_prefer256(i32 inreg %a, i32 inreg %b, i32 %c) "min-legal-vector-width"="256" "prefer-vector-width"="256" {194 %a0 = add i32 %a, %b195 %a1 = add i32 %a0, %c196 ret i32 %a1197}198