1266 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=SSE --check-prefix=SSE4A4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE415; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX16; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX27; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=VLX8 9; Make sure that we generate non-temporal stores for the test cases below.10; We use xorps for zeroing, so domain information isn't available anymore.11 12; Scalar versions (zeroing means we can this even for fp types).13 14define void @test_zero_f32(ptr %dst) {15; SSE-LABEL: test_zero_f32:16; SSE: # %bb.0:17; SSE-NEXT: xorl %eax, %eax18; SSE-NEXT: movntil %eax, (%rdi)19; SSE-NEXT: retq20;21; AVX-LABEL: test_zero_f32:22; AVX: # %bb.0:23; AVX-NEXT: xorl %eax, %eax24; AVX-NEXT: movntil %eax, (%rdi)25; AVX-NEXT: retq26;27; VLX-LABEL: test_zero_f32:28; VLX: # %bb.0:29; VLX-NEXT: xorl %eax, %eax30; VLX-NEXT: movntil %eax, (%rdi)31; VLX-NEXT: retq32 store float zeroinitializer, ptr %dst, align 1, !nontemporal !133 ret void34}35 36define void @test_zero_i32(ptr %dst) {37; SSE-LABEL: test_zero_i32:38; SSE: # %bb.0:39; SSE-NEXT: xorl %eax, %eax40; SSE-NEXT: movntil %eax, (%rdi)41; SSE-NEXT: retq42;43; AVX-LABEL: test_zero_i32:44; AVX: # %bb.0:45; AVX-NEXT: xorl %eax, %eax46; AVX-NEXT: movntil %eax, (%rdi)47; AVX-NEXT: retq48;49; VLX-LABEL: test_zero_i32:50; VLX: # %bb.0:51; VLX-NEXT: xorl %eax, %eax52; VLX-NEXT: movntil %eax, (%rdi)53; VLX-NEXT: retq54 store i32 zeroinitializer, ptr %dst, align 1, !nontemporal !155 ret void56}57 58define void @test_zero_f64(ptr %dst) {59; SSE-LABEL: test_zero_f64:60; SSE: # %bb.0:61; SSE-NEXT: xorl %eax, %eax62; SSE-NEXT: movntiq %rax, (%rdi)63; SSE-NEXT: retq64;65; AVX-LABEL: test_zero_f64:66; AVX: # %bb.0:67; AVX-NEXT: xorl %eax, %eax68; AVX-NEXT: movntiq %rax, (%rdi)69; AVX-NEXT: retq70;71; VLX-LABEL: test_zero_f64:72; VLX: # %bb.0:73; VLX-NEXT: xorl %eax, %eax74; VLX-NEXT: movntiq %rax, (%rdi)75; VLX-NEXT: retq76 store double zeroinitializer, ptr %dst, align 1, !nontemporal !177 ret void78}79 80define void @test_zero_i64(ptr %dst) {81; SSE-LABEL: test_zero_i64:82; SSE: # %bb.0:83; SSE-NEXT: xorl %eax, %eax84; SSE-NEXT: movntiq %rax, (%rdi)85; SSE-NEXT: retq86;87; AVX-LABEL: test_zero_i64:88; AVX: # %bb.0:89; AVX-NEXT: xorl %eax, %eax90; AVX-NEXT: movntiq %rax, (%rdi)91; AVX-NEXT: retq92;93; VLX-LABEL: test_zero_i64:94; VLX: # %bb.0:95; VLX-NEXT: xorl %eax, %eax96; VLX-NEXT: movntiq %rax, (%rdi)97; VLX-NEXT: retq98 store i64 zeroinitializer, ptr %dst, align 1, !nontemporal !199 ret void100}101 102; And now XMM versions.103 104define void @test_zero_v4f32(ptr %dst) {105; SSE-LABEL: test_zero_v4f32:106; SSE: # %bb.0:107; SSE-NEXT: xorps %xmm0, %xmm0108; SSE-NEXT: movntps %xmm0, (%rdi)109; SSE-NEXT: retq110;111; AVX-LABEL: test_zero_v4f32:112; AVX: # %bb.0:113; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0114; AVX-NEXT: vmovntps %xmm0, (%rdi)115; AVX-NEXT: retq116;117; VLX-LABEL: test_zero_v4f32:118; VLX: # %bb.0:119; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0120; VLX-NEXT: vmovntps %xmm0, (%rdi)121; VLX-NEXT: retq122 store <4 x float> zeroinitializer, ptr %dst, align 16, !nontemporal !1123 ret void124}125 126define void @test_zero_v4i32(ptr %dst) {127; SSE-LABEL: test_zero_v4i32:128; SSE: # %bb.0:129; SSE-NEXT: xorps %xmm0, %xmm0130; SSE-NEXT: movntps %xmm0, (%rdi)131; SSE-NEXT: retq132;133; AVX-LABEL: test_zero_v4i32:134; AVX: # %bb.0:135; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0136; AVX-NEXT: vmovntps %xmm0, (%rdi)137; AVX-NEXT: retq138;139; VLX-LABEL: test_zero_v4i32:140; VLX: # %bb.0:141; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0142; VLX-NEXT: vmovntps %xmm0, (%rdi)143; VLX-NEXT: retq144 store <4 x i32> zeroinitializer, ptr %dst, align 16, !nontemporal !1145 store <4 x i32> zeroinitializer, ptr %dst, align 16, !nontemporal !1146 ret void147}148 149define void @test_zero_v2f64(ptr %dst) {150; SSE-LABEL: test_zero_v2f64:151; SSE: # %bb.0:152; SSE-NEXT: xorps %xmm0, %xmm0153; SSE-NEXT: movntps %xmm0, (%rdi)154; SSE-NEXT: retq155;156; AVX-LABEL: test_zero_v2f64:157; AVX: # %bb.0:158; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0159; AVX-NEXT: vmovntps %xmm0, (%rdi)160; AVX-NEXT: retq161;162; VLX-LABEL: test_zero_v2f64:163; VLX: # %bb.0:164; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0165; VLX-NEXT: vmovntps %xmm0, (%rdi)166; VLX-NEXT: retq167 store <2 x double> zeroinitializer, ptr %dst, align 16, !nontemporal !1168 ret void169}170 171define void @test_zero_v2i64(ptr %dst) {172; SSE-LABEL: test_zero_v2i64:173; SSE: # %bb.0:174; SSE-NEXT: xorps %xmm0, %xmm0175; SSE-NEXT: movntps %xmm0, (%rdi)176; SSE-NEXT: retq177;178; AVX-LABEL: test_zero_v2i64:179; AVX: # %bb.0:180; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0181; AVX-NEXT: vmovntps %xmm0, (%rdi)182; AVX-NEXT: retq183;184; VLX-LABEL: test_zero_v2i64:185; VLX: # %bb.0:186; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0187; VLX-NEXT: vmovntps %xmm0, (%rdi)188; VLX-NEXT: retq189 store <2 x i64> zeroinitializer, ptr %dst, align 16, !nontemporal !1190 ret void191}192 193define void @test_zero_v8i16(ptr %dst) {194; SSE-LABEL: test_zero_v8i16:195; SSE: # %bb.0:196; SSE-NEXT: xorps %xmm0, %xmm0197; SSE-NEXT: movntps %xmm0, (%rdi)198; SSE-NEXT: retq199;200; AVX-LABEL: test_zero_v8i16:201; AVX: # %bb.0:202; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0203; AVX-NEXT: vmovntps %xmm0, (%rdi)204; AVX-NEXT: retq205;206; VLX-LABEL: test_zero_v8i16:207; VLX: # %bb.0:208; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0209; VLX-NEXT: vmovntps %xmm0, (%rdi)210; VLX-NEXT: retq211 store <8 x i16> zeroinitializer, ptr %dst, align 16, !nontemporal !1212 ret void213}214 215define void @test_zero_v16i8(ptr %dst) {216; SSE-LABEL: test_zero_v16i8:217; SSE: # %bb.0:218; SSE-NEXT: xorps %xmm0, %xmm0219; SSE-NEXT: movntps %xmm0, (%rdi)220; SSE-NEXT: retq221;222; AVX-LABEL: test_zero_v16i8:223; AVX: # %bb.0:224; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0225; AVX-NEXT: vmovntps %xmm0, (%rdi)226; AVX-NEXT: retq227;228; VLX-LABEL: test_zero_v16i8:229; VLX: # %bb.0:230; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0231; VLX-NEXT: vmovntps %xmm0, (%rdi)232; VLX-NEXT: retq233 store <16 x i8> zeroinitializer, ptr %dst, align 16, !nontemporal !1234 ret void235}236 237; And now YMM versions.238 239define void @test_zero_v8f32(ptr %dst) {240; SSE-LABEL: test_zero_v8f32:241; SSE: # %bb.0:242; SSE-NEXT: xorps %xmm0, %xmm0243; SSE-NEXT: movntps %xmm0, 16(%rdi)244; SSE-NEXT: movntps %xmm0, (%rdi)245; SSE-NEXT: retq246;247; AVX-LABEL: test_zero_v8f32:248; AVX: # %bb.0:249; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0250; AVX-NEXT: vmovntps %ymm0, (%rdi)251; AVX-NEXT: vzeroupper252; AVX-NEXT: retq253;254; VLX-LABEL: test_zero_v8f32:255; VLX: # %bb.0:256; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0257; VLX-NEXT: vmovntps %ymm0, (%rdi)258; VLX-NEXT: vzeroupper259; VLX-NEXT: retq260 store <8 x float> zeroinitializer, ptr %dst, align 32, !nontemporal !1261 ret void262}263 264define void @test_zero_v8i32(ptr %dst) {265; SSE-LABEL: test_zero_v8i32:266; SSE: # %bb.0:267; SSE-NEXT: xorps %xmm0, %xmm0268; SSE-NEXT: movntps %xmm0, 16(%rdi)269; SSE-NEXT: movntps %xmm0, (%rdi)270; SSE-NEXT: retq271;272; AVX-LABEL: test_zero_v8i32:273; AVX: # %bb.0:274; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0275; AVX-NEXT: vmovntps %ymm0, (%rdi)276; AVX-NEXT: vzeroupper277; AVX-NEXT: retq278;279; VLX-LABEL: test_zero_v8i32:280; VLX: # %bb.0:281; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0282; VLX-NEXT: vmovntps %ymm0, (%rdi)283; VLX-NEXT: vzeroupper284; VLX-NEXT: retq285 store <8 x i32> zeroinitializer, ptr %dst, align 32, !nontemporal !1286 ret void287}288 289define void @test_zero_v4f64(ptr %dst) {290; SSE-LABEL: test_zero_v4f64:291; SSE: # %bb.0:292; SSE-NEXT: xorps %xmm0, %xmm0293; SSE-NEXT: movntps %xmm0, 16(%rdi)294; SSE-NEXT: movntps %xmm0, (%rdi)295; SSE-NEXT: retq296;297; AVX-LABEL: test_zero_v4f64:298; AVX: # %bb.0:299; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0300; AVX-NEXT: vmovntps %ymm0, (%rdi)301; AVX-NEXT: vzeroupper302; AVX-NEXT: retq303;304; VLX-LABEL: test_zero_v4f64:305; VLX: # %bb.0:306; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0307; VLX-NEXT: vmovntps %ymm0, (%rdi)308; VLX-NEXT: vzeroupper309; VLX-NEXT: retq310 store <4 x double> zeroinitializer, ptr %dst, align 32, !nontemporal !1311 ret void312}313 314define void @test_zero_v4i64(ptr %dst) {315; SSE-LABEL: test_zero_v4i64:316; SSE: # %bb.0:317; SSE-NEXT: xorps %xmm0, %xmm0318; SSE-NEXT: movntps %xmm0, 16(%rdi)319; SSE-NEXT: movntps %xmm0, (%rdi)320; SSE-NEXT: retq321;322; AVX-LABEL: test_zero_v4i64:323; AVX: # %bb.0:324; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0325; AVX-NEXT: vmovntps %ymm0, (%rdi)326; AVX-NEXT: vzeroupper327; AVX-NEXT: retq328;329; VLX-LABEL: test_zero_v4i64:330; VLX: # %bb.0:331; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0332; VLX-NEXT: vmovntps %ymm0, (%rdi)333; VLX-NEXT: vzeroupper334; VLX-NEXT: retq335 store <4 x i64> zeroinitializer, ptr %dst, align 32, !nontemporal !1336 ret void337}338 339define void @test_zero_v16i16(ptr %dst) {340; SSE-LABEL: test_zero_v16i16:341; SSE: # %bb.0:342; SSE-NEXT: xorps %xmm0, %xmm0343; SSE-NEXT: movntps %xmm0, 16(%rdi)344; SSE-NEXT: movntps %xmm0, (%rdi)345; SSE-NEXT: retq346;347; AVX-LABEL: test_zero_v16i16:348; AVX: # %bb.0:349; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0350; AVX-NEXT: vmovntps %ymm0, (%rdi)351; AVX-NEXT: vzeroupper352; AVX-NEXT: retq353;354; VLX-LABEL: test_zero_v16i16:355; VLX: # %bb.0:356; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0357; VLX-NEXT: vmovntps %ymm0, (%rdi)358; VLX-NEXT: vzeroupper359; VLX-NEXT: retq360 store <16 x i16> zeroinitializer, ptr %dst, align 32, !nontemporal !1361 ret void362}363 364define void @test_zero_v32i8(ptr %dst) {365; SSE-LABEL: test_zero_v32i8:366; SSE: # %bb.0:367; SSE-NEXT: xorps %xmm0, %xmm0368; SSE-NEXT: movntps %xmm0, 16(%rdi)369; SSE-NEXT: movntps %xmm0, (%rdi)370; SSE-NEXT: retq371;372; AVX-LABEL: test_zero_v32i8:373; AVX: # %bb.0:374; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0375; AVX-NEXT: vmovntps %ymm0, (%rdi)376; AVX-NEXT: vzeroupper377; AVX-NEXT: retq378;379; VLX-LABEL: test_zero_v32i8:380; VLX: # %bb.0:381; VLX-NEXT: vxorps %xmm0, %xmm0, %xmm0382; VLX-NEXT: vmovntps %ymm0, (%rdi)383; VLX-NEXT: vzeroupper384; VLX-NEXT: retq385 store <32 x i8> zeroinitializer, ptr %dst, align 32, !nontemporal !1386 ret void387}388 389 390; Check that we also handle arguments. Here the type survives longer.391 392; Scalar versions.393 394define void @test_arg_f32(float %arg, ptr %dst) {395; SSE2-LABEL: test_arg_f32:396; SSE2: # %bb.0:397; SSE2-NEXT: movss %xmm0, (%rdi)398; SSE2-NEXT: retq399;400; SSE4A-LABEL: test_arg_f32:401; SSE4A: # %bb.0:402; SSE4A-NEXT: movntss %xmm0, (%rdi)403; SSE4A-NEXT: retq404;405; SSE41-LABEL: test_arg_f32:406; SSE41: # %bb.0:407; SSE41-NEXT: movss %xmm0, (%rdi)408; SSE41-NEXT: retq409;410; AVX-LABEL: test_arg_f32:411; AVX: # %bb.0:412; AVX-NEXT: vmovss %xmm0, (%rdi)413; AVX-NEXT: retq414;415; VLX-LABEL: test_arg_f32:416; VLX: # %bb.0:417; VLX-NEXT: vmovss %xmm0, (%rdi)418; VLX-NEXT: retq419 store float %arg, ptr %dst, align 1, !nontemporal !1420 ret void421}422 423define void @test_arg_i32(i32 %arg, ptr %dst) {424; SSE-LABEL: test_arg_i32:425; SSE: # %bb.0:426; SSE-NEXT: movntil %edi, (%rsi)427; SSE-NEXT: retq428;429; AVX-LABEL: test_arg_i32:430; AVX: # %bb.0:431; AVX-NEXT: movntil %edi, (%rsi)432; AVX-NEXT: retq433;434; VLX-LABEL: test_arg_i32:435; VLX: # %bb.0:436; VLX-NEXT: movntil %edi, (%rsi)437; VLX-NEXT: retq438 store i32 %arg, ptr %dst, align 1, !nontemporal !1439 ret void440}441 442define void @test_arg_f64(double %arg, ptr %dst) {443; SSE2-LABEL: test_arg_f64:444; SSE2: # %bb.0:445; SSE2-NEXT: movsd %xmm0, (%rdi)446; SSE2-NEXT: retq447;448; SSE4A-LABEL: test_arg_f64:449; SSE4A: # %bb.0:450; SSE4A-NEXT: movntsd %xmm0, (%rdi)451; SSE4A-NEXT: retq452;453; SSE41-LABEL: test_arg_f64:454; SSE41: # %bb.0:455; SSE41-NEXT: movsd %xmm0, (%rdi)456; SSE41-NEXT: retq457;458; AVX-LABEL: test_arg_f64:459; AVX: # %bb.0:460; AVX-NEXT: vmovsd %xmm0, (%rdi)461; AVX-NEXT: retq462;463; VLX-LABEL: test_arg_f64:464; VLX: # %bb.0:465; VLX-NEXT: vmovsd %xmm0, (%rdi)466; VLX-NEXT: retq467 store double %arg, ptr %dst, align 1, !nontemporal !1468 ret void469}470 471define void @test_arg_i64(i64 %arg, ptr %dst) {472; SSE-LABEL: test_arg_i64:473; SSE: # %bb.0:474; SSE-NEXT: movntiq %rdi, (%rsi)475; SSE-NEXT: retq476;477; AVX-LABEL: test_arg_i64:478; AVX: # %bb.0:479; AVX-NEXT: movntiq %rdi, (%rsi)480; AVX-NEXT: retq481;482; VLX-LABEL: test_arg_i64:483; VLX: # %bb.0:484; VLX-NEXT: movntiq %rdi, (%rsi)485; VLX-NEXT: retq486 store i64 %arg, ptr %dst, align 1, !nontemporal !1487 ret void488}489 490; Extract versions491 492define void @test_extract_f32(<4 x float> %arg, ptr %dst) {493; SSE2-LABEL: test_extract_f32:494; SSE2: # %bb.0:495; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]496; SSE2-NEXT: movss %xmm0, (%rdi)497; SSE2-NEXT: retq498;499; SSE4A-LABEL: test_extract_f32:500; SSE4A: # %bb.0:501; SSE4A-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]502; SSE4A-NEXT: movntss %xmm0, (%rdi)503; SSE4A-NEXT: retq504;505; SSE41-LABEL: test_extract_f32:506; SSE41: # %bb.0:507; SSE41-NEXT: extractps $1, %xmm0, %eax508; SSE41-NEXT: movntil %eax, (%rdi)509; SSE41-NEXT: retq510;511; AVX-LABEL: test_extract_f32:512; AVX: # %bb.0:513; AVX-NEXT: vextractps $1, %xmm0, %eax514; AVX-NEXT: movntil %eax, (%rdi)515; AVX-NEXT: retq516;517; VLX-LABEL: test_extract_f32:518; VLX: # %bb.0:519; VLX-NEXT: vextractps $1, %xmm0, %eax520; VLX-NEXT: movntil %eax, (%rdi)521; VLX-NEXT: retq522 %1 = extractelement <4 x float> %arg, i32 1523 store float %1, ptr %dst, align 1, !nontemporal !1524 ret void525}526 527define void @test_extract_i32(<4 x i32> %arg, ptr %dst) {528; SSE2-LABEL: test_extract_i32:529; SSE2: # %bb.0:530; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]531; SSE2-NEXT: movd %xmm0, %eax532; SSE2-NEXT: movntil %eax, (%rdi)533; SSE2-NEXT: retq534;535; SSE4A-LABEL: test_extract_i32:536; SSE4A: # %bb.0:537; SSE4A-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]538; SSE4A-NEXT: movd %xmm0, %eax539; SSE4A-NEXT: movntil %eax, (%rdi)540; SSE4A-NEXT: retq541;542; SSE41-LABEL: test_extract_i32:543; SSE41: # %bb.0:544; SSE41-NEXT: extractps $1, %xmm0, %eax545; SSE41-NEXT: movntil %eax, (%rdi)546; SSE41-NEXT: retq547;548; AVX-LABEL: test_extract_i32:549; AVX: # %bb.0:550; AVX-NEXT: vextractps $1, %xmm0, %eax551; AVX-NEXT: movntil %eax, (%rdi)552; AVX-NEXT: retq553;554; VLX-LABEL: test_extract_i32:555; VLX: # %bb.0:556; VLX-NEXT: vextractps $1, %xmm0, %eax557; VLX-NEXT: movntil %eax, (%rdi)558; VLX-NEXT: retq559 %1 = extractelement <4 x i32> %arg, i32 1560 store i32 %1, ptr %dst, align 1, !nontemporal !1561 ret void562}563 564define void @test_extract_f64(<2 x double> %arg, ptr %dst) {565; SSE2-LABEL: test_extract_f64:566; SSE2: # %bb.0:567; SSE2-NEXT: movhps %xmm0, (%rdi)568; SSE2-NEXT: retq569;570; SSE4A-LABEL: test_extract_f64:571; SSE4A: # %bb.0:572; SSE4A-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]573; SSE4A-NEXT: movntsd %xmm0, (%rdi)574; SSE4A-NEXT: retq575;576; SSE41-LABEL: test_extract_f64:577; SSE41: # %bb.0:578; SSE41-NEXT: movhps %xmm0, (%rdi)579; SSE41-NEXT: retq580;581; AVX-LABEL: test_extract_f64:582; AVX: # %bb.0:583; AVX-NEXT: vmovhps %xmm0, (%rdi)584; AVX-NEXT: retq585;586; VLX-LABEL: test_extract_f64:587; VLX: # %bb.0:588; VLX-NEXT: vmovhps %xmm0, (%rdi)589; VLX-NEXT: retq590 %1 = extractelement <2 x double> %arg, i32 1591 store double %1, ptr %dst, align 1, !nontemporal !1592 ret void593}594 595define void @test_extract_i64(<2 x i64> %arg, ptr %dst) {596; SSE2-LABEL: test_extract_i64:597; SSE2: # %bb.0:598; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]599; SSE2-NEXT: movq %xmm0, %rax600; SSE2-NEXT: movntiq %rax, (%rdi)601; SSE2-NEXT: retq602;603; SSE4A-LABEL: test_extract_i64:604; SSE4A: # %bb.0:605; SSE4A-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]606; SSE4A-NEXT: movq %xmm0, %rax607; SSE4A-NEXT: movntiq %rax, (%rdi)608; SSE4A-NEXT: retq609;610; SSE41-LABEL: test_extract_i64:611; SSE41: # %bb.0:612; SSE41-NEXT: pextrq $1, %xmm0, %rax613; SSE41-NEXT: movntiq %rax, (%rdi)614; SSE41-NEXT: retq615;616; AVX-LABEL: test_extract_i64:617; AVX: # %bb.0:618; AVX-NEXT: vpextrq $1, %xmm0, %rax619; AVX-NEXT: movntiq %rax, (%rdi)620; AVX-NEXT: retq621;622; VLX-LABEL: test_extract_i64:623; VLX: # %bb.0:624; VLX-NEXT: vpextrq $1, %xmm0, %rax625; VLX-NEXT: movntiq %rax, (%rdi)626; VLX-NEXT: retq627 %1 = extractelement <2 x i64> %arg, i32 1628 store i64 %1, ptr %dst, align 1, !nontemporal !1629 ret void630}631 632; And now XMM versions.633 634define void @test_arg_v4f32(<4 x float> %arg, ptr %dst) {635; SSE-LABEL: test_arg_v4f32:636; SSE: # %bb.0:637; SSE-NEXT: movntps %xmm0, (%rdi)638; SSE-NEXT: retq639;640; AVX-LABEL: test_arg_v4f32:641; AVX: # %bb.0:642; AVX-NEXT: vmovntps %xmm0, (%rdi)643; AVX-NEXT: retq644;645; VLX-LABEL: test_arg_v4f32:646; VLX: # %bb.0:647; VLX-NEXT: vmovntps %xmm0, (%rdi)648; VLX-NEXT: retq649 store <4 x float> %arg, ptr %dst, align 16, !nontemporal !1650 ret void651}652 653define void @test_arg_v4i32(<4 x i32> %arg, ptr %dst) {654; SSE-LABEL: test_arg_v4i32:655; SSE: # %bb.0:656; SSE-NEXT: movntps %xmm0, (%rdi)657; SSE-NEXT: retq658;659; AVX-LABEL: test_arg_v4i32:660; AVX: # %bb.0:661; AVX-NEXT: vmovntps %xmm0, (%rdi)662; AVX-NEXT: retq663;664; VLX-LABEL: test_arg_v4i32:665; VLX: # %bb.0:666; VLX-NEXT: vmovntps %xmm0, (%rdi)667; VLX-NEXT: retq668 store <4 x i32> %arg, ptr %dst, align 16, !nontemporal !1669 ret void670}671 672define void @test_arg_v2f64(<2 x double> %arg, ptr %dst) {673; SSE-LABEL: test_arg_v2f64:674; SSE: # %bb.0:675; SSE-NEXT: movntps %xmm0, (%rdi)676; SSE-NEXT: retq677;678; AVX-LABEL: test_arg_v2f64:679; AVX: # %bb.0:680; AVX-NEXT: vmovntps %xmm0, (%rdi)681; AVX-NEXT: retq682;683; VLX-LABEL: test_arg_v2f64:684; VLX: # %bb.0:685; VLX-NEXT: vmovntps %xmm0, (%rdi)686; VLX-NEXT: retq687 store <2 x double> %arg, ptr %dst, align 16, !nontemporal !1688 ret void689}690 691define void @test_arg_v2i64(<2 x i64> %arg, ptr %dst) {692; SSE-LABEL: test_arg_v2i64:693; SSE: # %bb.0:694; SSE-NEXT: movntps %xmm0, (%rdi)695; SSE-NEXT: retq696;697; AVX-LABEL: test_arg_v2i64:698; AVX: # %bb.0:699; AVX-NEXT: vmovntps %xmm0, (%rdi)700; AVX-NEXT: retq701;702; VLX-LABEL: test_arg_v2i64:703; VLX: # %bb.0:704; VLX-NEXT: vmovntps %xmm0, (%rdi)705; VLX-NEXT: retq706 store <2 x i64> %arg, ptr %dst, align 16, !nontemporal !1707 ret void708}709 710define void @test_arg_v8i16(<8 x i16> %arg, ptr %dst) {711; SSE-LABEL: test_arg_v8i16:712; SSE: # %bb.0:713; SSE-NEXT: movntps %xmm0, (%rdi)714; SSE-NEXT: retq715;716; AVX-LABEL: test_arg_v8i16:717; AVX: # %bb.0:718; AVX-NEXT: vmovntps %xmm0, (%rdi)719; AVX-NEXT: retq720;721; VLX-LABEL: test_arg_v8i16:722; VLX: # %bb.0:723; VLX-NEXT: vmovntps %xmm0, (%rdi)724; VLX-NEXT: retq725 store <8 x i16> %arg, ptr %dst, align 16, !nontemporal !1726 ret void727}728 729define void @test_arg_v16i8(<16 x i8> %arg, ptr %dst) {730; SSE-LABEL: test_arg_v16i8:731; SSE: # %bb.0:732; SSE-NEXT: movntps %xmm0, (%rdi)733; SSE-NEXT: retq734;735; AVX-LABEL: test_arg_v16i8:736; AVX: # %bb.0:737; AVX-NEXT: vmovntps %xmm0, (%rdi)738; AVX-NEXT: retq739;740; VLX-LABEL: test_arg_v16i8:741; VLX: # %bb.0:742; VLX-NEXT: vmovntps %xmm0, (%rdi)743; VLX-NEXT: retq744 store <16 x i8> %arg, ptr %dst, align 16, !nontemporal !1745 ret void746}747 748; And now YMM versions.749 750define void @test_arg_v8f32(<8 x float> %arg, ptr %dst) {751; SSE-LABEL: test_arg_v8f32:752; SSE: # %bb.0:753; SSE-NEXT: movntps %xmm1, 16(%rdi)754; SSE-NEXT: movntps %xmm0, (%rdi)755; SSE-NEXT: retq756;757; AVX-LABEL: test_arg_v8f32:758; AVX: # %bb.0:759; AVX-NEXT: vmovntps %ymm0, (%rdi)760; AVX-NEXT: vzeroupper761; AVX-NEXT: retq762;763; VLX-LABEL: test_arg_v8f32:764; VLX: # %bb.0:765; VLX-NEXT: vmovntps %ymm0, (%rdi)766; VLX-NEXT: vzeroupper767; VLX-NEXT: retq768 store <8 x float> %arg, ptr %dst, align 32, !nontemporal !1769 ret void770}771 772define void @test_arg_v8i32(<8 x i32> %arg, ptr %dst) {773; SSE-LABEL: test_arg_v8i32:774; SSE: # %bb.0:775; SSE-NEXT: movntps %xmm1, 16(%rdi)776; SSE-NEXT: movntps %xmm0, (%rdi)777; SSE-NEXT: retq778;779; AVX-LABEL: test_arg_v8i32:780; AVX: # %bb.0:781; AVX-NEXT: vmovntps %ymm0, (%rdi)782; AVX-NEXT: vzeroupper783; AVX-NEXT: retq784;785; VLX-LABEL: test_arg_v8i32:786; VLX: # %bb.0:787; VLX-NEXT: vmovntps %ymm0, (%rdi)788; VLX-NEXT: vzeroupper789; VLX-NEXT: retq790 store <8 x i32> %arg, ptr %dst, align 32, !nontemporal !1791 ret void792}793 794define void @test_arg_v4f64(<4 x double> %arg, ptr %dst) {795; SSE-LABEL: test_arg_v4f64:796; SSE: # %bb.0:797; SSE-NEXT: movntps %xmm1, 16(%rdi)798; SSE-NEXT: movntps %xmm0, (%rdi)799; SSE-NEXT: retq800;801; AVX-LABEL: test_arg_v4f64:802; AVX: # %bb.0:803; AVX-NEXT: vmovntps %ymm0, (%rdi)804; AVX-NEXT: vzeroupper805; AVX-NEXT: retq806;807; VLX-LABEL: test_arg_v4f64:808; VLX: # %bb.0:809; VLX-NEXT: vmovntps %ymm0, (%rdi)810; VLX-NEXT: vzeroupper811; VLX-NEXT: retq812 store <4 x double> %arg, ptr %dst, align 32, !nontemporal !1813 ret void814}815 816define void @test_arg_v4i64(<4 x i64> %arg, ptr %dst) {817; SSE-LABEL: test_arg_v4i64:818; SSE: # %bb.0:819; SSE-NEXT: movntps %xmm1, 16(%rdi)820; SSE-NEXT: movntps %xmm0, (%rdi)821; SSE-NEXT: retq822;823; AVX-LABEL: test_arg_v4i64:824; AVX: # %bb.0:825; AVX-NEXT: vmovntps %ymm0, (%rdi)826; AVX-NEXT: vzeroupper827; AVX-NEXT: retq828;829; VLX-LABEL: test_arg_v4i64:830; VLX: # %bb.0:831; VLX-NEXT: vmovntps %ymm0, (%rdi)832; VLX-NEXT: vzeroupper833; VLX-NEXT: retq834 store <4 x i64> %arg, ptr %dst, align 32, !nontemporal !1835 ret void836}837 838define void @test_arg_v16i16(<16 x i16> %arg, ptr %dst) {839; SSE-LABEL: test_arg_v16i16:840; SSE: # %bb.0:841; SSE-NEXT: movntps %xmm1, 16(%rdi)842; SSE-NEXT: movntps %xmm0, (%rdi)843; SSE-NEXT: retq844;845; AVX-LABEL: test_arg_v16i16:846; AVX: # %bb.0:847; AVX-NEXT: vmovntps %ymm0, (%rdi)848; AVX-NEXT: vzeroupper849; AVX-NEXT: retq850;851; VLX-LABEL: test_arg_v16i16:852; VLX: # %bb.0:853; VLX-NEXT: vmovntps %ymm0, (%rdi)854; VLX-NEXT: vzeroupper855; VLX-NEXT: retq856 store <16 x i16> %arg, ptr %dst, align 32, !nontemporal !1857 ret void858}859 860define void @test_arg_v32i8(<32 x i8> %arg, ptr %dst) {861; SSE-LABEL: test_arg_v32i8:862; SSE: # %bb.0:863; SSE-NEXT: movntps %xmm1, 16(%rdi)864; SSE-NEXT: movntps %xmm0, (%rdi)865; SSE-NEXT: retq866;867; AVX-LABEL: test_arg_v32i8:868; AVX: # %bb.0:869; AVX-NEXT: vmovntps %ymm0, (%rdi)870; AVX-NEXT: vzeroupper871; AVX-NEXT: retq872;873; VLX-LABEL: test_arg_v32i8:874; VLX: # %bb.0:875; VLX-NEXT: vmovntps %ymm0, (%rdi)876; VLX-NEXT: vzeroupper877; VLX-NEXT: retq878 store <32 x i8> %arg, ptr %dst, align 32, !nontemporal !1879 ret void880}881 882 883; Now check that if the execution domain is trivially visible, we use it.884; We use an add to make the type survive all the way to the MOVNT.885 886define void @test_op_v4f32(<4 x float> %a, <4 x float> %b, ptr %dst) {887; SSE-LABEL: test_op_v4f32:888; SSE: # %bb.0:889; SSE-NEXT: addps %xmm1, %xmm0890; SSE-NEXT: movntps %xmm0, (%rdi)891; SSE-NEXT: retq892;893; AVX-LABEL: test_op_v4f32:894; AVX: # %bb.0:895; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0896; AVX-NEXT: vmovntps %xmm0, (%rdi)897; AVX-NEXT: retq898;899; VLX-LABEL: test_op_v4f32:900; VLX: # %bb.0:901; VLX-NEXT: vaddps %xmm1, %xmm0, %xmm0902; VLX-NEXT: vmovntps %xmm0, (%rdi)903; VLX-NEXT: retq904 %r = fadd <4 x float> %a, %b905 store <4 x float> %r, ptr %dst, align 16, !nontemporal !1906 ret void907}908 909define void @test_op_v4i32(<4 x i32> %a, <4 x i32> %b, ptr %dst) {910; SSE-LABEL: test_op_v4i32:911; SSE: # %bb.0:912; SSE-NEXT: paddd %xmm1, %xmm0913; SSE-NEXT: movntdq %xmm0, (%rdi)914; SSE-NEXT: retq915;916; AVX-LABEL: test_op_v4i32:917; AVX: # %bb.0:918; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0919; AVX-NEXT: vmovntdq %xmm0, (%rdi)920; AVX-NEXT: retq921;922; VLX-LABEL: test_op_v4i32:923; VLX: # %bb.0:924; VLX-NEXT: vpaddd %xmm1, %xmm0, %xmm0925; VLX-NEXT: vmovntdq %xmm0, (%rdi)926; VLX-NEXT: retq927 %r = add <4 x i32> %a, %b928 store <4 x i32> %r, ptr %dst, align 16, !nontemporal !1929 ret void930}931 932define void @test_op_v2f64(<2 x double> %a, <2 x double> %b, ptr %dst) {933; SSE-LABEL: test_op_v2f64:934; SSE: # %bb.0:935; SSE-NEXT: addpd %xmm1, %xmm0936; SSE-NEXT: movntpd %xmm0, (%rdi)937; SSE-NEXT: retq938;939; AVX-LABEL: test_op_v2f64:940; AVX: # %bb.0:941; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0942; AVX-NEXT: vmovntpd %xmm0, (%rdi)943; AVX-NEXT: retq944;945; VLX-LABEL: test_op_v2f64:946; VLX: # %bb.0:947; VLX-NEXT: vaddpd %xmm1, %xmm0, %xmm0948; VLX-NEXT: vmovntpd %xmm0, (%rdi)949; VLX-NEXT: retq950 %r = fadd <2 x double> %a, %b951 store <2 x double> %r, ptr %dst, align 16, !nontemporal !1952 ret void953}954 955define void @test_op_v2i64(<2 x i64> %a, <2 x i64> %b, ptr %dst) {956; SSE-LABEL: test_op_v2i64:957; SSE: # %bb.0:958; SSE-NEXT: paddq %xmm1, %xmm0959; SSE-NEXT: movntdq %xmm0, (%rdi)960; SSE-NEXT: retq961;962; AVX-LABEL: test_op_v2i64:963; AVX: # %bb.0:964; AVX-NEXT: vpaddq %xmm1, %xmm0, %xmm0965; AVX-NEXT: vmovntdq %xmm0, (%rdi)966; AVX-NEXT: retq967;968; VLX-LABEL: test_op_v2i64:969; VLX: # %bb.0:970; VLX-NEXT: vpaddq %xmm1, %xmm0, %xmm0971; VLX-NEXT: vmovntdq %xmm0, (%rdi)972; VLX-NEXT: retq973 %r = add <2 x i64> %a, %b974 store <2 x i64> %r, ptr %dst, align 16, !nontemporal !1975 ret void976}977 978define void @test_op_v8i16(<8 x i16> %a, <8 x i16> %b, ptr %dst) {979; SSE-LABEL: test_op_v8i16:980; SSE: # %bb.0:981; SSE-NEXT: paddw %xmm1, %xmm0982; SSE-NEXT: movntdq %xmm0, (%rdi)983; SSE-NEXT: retq984;985; AVX-LABEL: test_op_v8i16:986; AVX: # %bb.0:987; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0988; AVX-NEXT: vmovntdq %xmm0, (%rdi)989; AVX-NEXT: retq990;991; VLX-LABEL: test_op_v8i16:992; VLX: # %bb.0:993; VLX-NEXT: vpaddw %xmm1, %xmm0, %xmm0994; VLX-NEXT: vmovntdq %xmm0, (%rdi)995; VLX-NEXT: retq996 %r = add <8 x i16> %a, %b997 store <8 x i16> %r, ptr %dst, align 16, !nontemporal !1998 ret void999}1000 1001define void @test_op_v16i8(<16 x i8> %a, <16 x i8> %b, ptr %dst) {1002; SSE-LABEL: test_op_v16i8:1003; SSE: # %bb.0:1004; SSE-NEXT: paddb %xmm1, %xmm01005; SSE-NEXT: movntdq %xmm0, (%rdi)1006; SSE-NEXT: retq1007;1008; AVX-LABEL: test_op_v16i8:1009; AVX: # %bb.0:1010; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm01011; AVX-NEXT: vmovntdq %xmm0, (%rdi)1012; AVX-NEXT: retq1013;1014; VLX-LABEL: test_op_v16i8:1015; VLX: # %bb.0:1016; VLX-NEXT: vpaddb %xmm1, %xmm0, %xmm01017; VLX-NEXT: vmovntdq %xmm0, (%rdi)1018; VLX-NEXT: retq1019 %r = add <16 x i8> %a, %b1020 store <16 x i8> %r, ptr %dst, align 16, !nontemporal !11021 ret void1022}1023 1024; And now YMM versions.1025 1026define void @test_op_v8f32(<8 x float> %a, <8 x float> %b, ptr %dst) {1027; SSE-LABEL: test_op_v8f32:1028; SSE: # %bb.0:1029; SSE-NEXT: addps %xmm2, %xmm01030; SSE-NEXT: addps %xmm3, %xmm11031; SSE-NEXT: movntps %xmm1, 16(%rdi)1032; SSE-NEXT: movntps %xmm0, (%rdi)1033; SSE-NEXT: retq1034;1035; AVX-LABEL: test_op_v8f32:1036; AVX: # %bb.0:1037; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm01038; AVX-NEXT: vmovntps %ymm0, (%rdi)1039; AVX-NEXT: vzeroupper1040; AVX-NEXT: retq1041;1042; VLX-LABEL: test_op_v8f32:1043; VLX: # %bb.0:1044; VLX-NEXT: vaddps %ymm1, %ymm0, %ymm01045; VLX-NEXT: vmovntps %ymm0, (%rdi)1046; VLX-NEXT: vzeroupper1047; VLX-NEXT: retq1048 %r = fadd <8 x float> %a, %b1049 store <8 x float> %r, ptr %dst, align 32, !nontemporal !11050 ret void1051}1052 1053define void @test_op_v8i32(<8 x i32> %a, <8 x i32> %b, ptr %dst) {1054; SSE-LABEL: test_op_v8i32:1055; SSE: # %bb.0:1056; SSE-NEXT: paddd %xmm2, %xmm01057; SSE-NEXT: paddd %xmm3, %xmm11058; SSE-NEXT: movntdq %xmm1, 16(%rdi)1059; SSE-NEXT: movntdq %xmm0, (%rdi)1060; SSE-NEXT: retq1061;1062; AVX1-LABEL: test_op_v8i32:1063; AVX1: # %bb.0:1064; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm21065; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm11066; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01067; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm01068; AVX1-NEXT: vmovntdq %xmm0, 16(%rdi)1069; AVX1-NEXT: vmovntdq %xmm2, (%rdi)1070; AVX1-NEXT: vzeroupper1071; AVX1-NEXT: retq1072;1073; AVX2-LABEL: test_op_v8i32:1074; AVX2: # %bb.0:1075; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm01076; AVX2-NEXT: vmovntdq %ymm0, (%rdi)1077; AVX2-NEXT: vzeroupper1078; AVX2-NEXT: retq1079;1080; VLX-LABEL: test_op_v8i32:1081; VLX: # %bb.0:1082; VLX-NEXT: vpaddd %ymm1, %ymm0, %ymm01083; VLX-NEXT: vmovntdq %ymm0, (%rdi)1084; VLX-NEXT: vzeroupper1085; VLX-NEXT: retq1086 %r = add <8 x i32> %a, %b1087 store <8 x i32> %r, ptr %dst, align 32, !nontemporal !11088 ret void1089}1090 1091define void @test_op_v4f64(<4 x double> %a, <4 x double> %b, ptr %dst) {1092; SSE-LABEL: test_op_v4f64:1093; SSE: # %bb.0:1094; SSE-NEXT: addpd %xmm2, %xmm01095; SSE-NEXT: addpd %xmm3, %xmm11096; SSE-NEXT: movntpd %xmm1, 16(%rdi)1097; SSE-NEXT: movntpd %xmm0, (%rdi)1098; SSE-NEXT: retq1099;1100; AVX-LABEL: test_op_v4f64:1101; AVX: # %bb.0:1102; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm01103; AVX-NEXT: vmovntpd %ymm0, (%rdi)1104; AVX-NEXT: vzeroupper1105; AVX-NEXT: retq1106;1107; VLX-LABEL: test_op_v4f64:1108; VLX: # %bb.0:1109; VLX-NEXT: vaddpd %ymm1, %ymm0, %ymm01110; VLX-NEXT: vmovntpd %ymm0, (%rdi)1111; VLX-NEXT: vzeroupper1112; VLX-NEXT: retq1113 %r = fadd <4 x double> %a, %b1114 store <4 x double> %r, ptr %dst, align 32, !nontemporal !11115 ret void1116}1117 1118define void @test_op_v4i64(<4 x i64> %a, <4 x i64> %b, ptr %dst) {1119; SSE-LABEL: test_op_v4i64:1120; SSE: # %bb.0:1121; SSE-NEXT: paddq %xmm2, %xmm01122; SSE-NEXT: paddq %xmm3, %xmm11123; SSE-NEXT: movntdq %xmm1, 16(%rdi)1124; SSE-NEXT: movntdq %xmm0, (%rdi)1125; SSE-NEXT: retq1126;1127; AVX1-LABEL: test_op_v4i64:1128; AVX1: # %bb.0:1129; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm21130; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm11131; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01132; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm01133; AVX1-NEXT: vmovntdq %xmm0, 16(%rdi)1134; AVX1-NEXT: vmovntdq %xmm2, (%rdi)1135; AVX1-NEXT: vzeroupper1136; AVX1-NEXT: retq1137;1138; AVX2-LABEL: test_op_v4i64:1139; AVX2: # %bb.0:1140; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm01141; AVX2-NEXT: vmovntdq %ymm0, (%rdi)1142; AVX2-NEXT: vzeroupper1143; AVX2-NEXT: retq1144;1145; VLX-LABEL: test_op_v4i64:1146; VLX: # %bb.0:1147; VLX-NEXT: vpaddq %ymm1, %ymm0, %ymm01148; VLX-NEXT: vmovntdq %ymm0, (%rdi)1149; VLX-NEXT: vzeroupper1150; VLX-NEXT: retq1151 %r = add <4 x i64> %a, %b1152 store <4 x i64> %r, ptr %dst, align 32, !nontemporal !11153 ret void1154}1155 1156define void @test_op_v16i16(<16 x i16> %a, <16 x i16> %b, ptr %dst) {1157; SSE-LABEL: test_op_v16i16:1158; SSE: # %bb.0:1159; SSE-NEXT: paddw %xmm2, %xmm01160; SSE-NEXT: paddw %xmm3, %xmm11161; SSE-NEXT: movntdq %xmm1, 16(%rdi)1162; SSE-NEXT: movntdq %xmm0, (%rdi)1163; SSE-NEXT: retq1164;1165; AVX1-LABEL: test_op_v16i16:1166; AVX1: # %bb.0:1167; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm21168; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm11169; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01170; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm01171; AVX1-NEXT: vmovntdq %xmm0, 16(%rdi)1172; AVX1-NEXT: vmovntdq %xmm2, (%rdi)1173; AVX1-NEXT: vzeroupper1174; AVX1-NEXT: retq1175;1176; AVX2-LABEL: test_op_v16i16:1177; AVX2: # %bb.0:1178; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm01179; AVX2-NEXT: vmovntdq %ymm0, (%rdi)1180; AVX2-NEXT: vzeroupper1181; AVX2-NEXT: retq1182;1183; VLX-LABEL: test_op_v16i16:1184; VLX: # %bb.0:1185; VLX-NEXT: vpaddw %ymm1, %ymm0, %ymm01186; VLX-NEXT: vmovntdq %ymm0, (%rdi)1187; VLX-NEXT: vzeroupper1188; VLX-NEXT: retq1189 %r = add <16 x i16> %a, %b1190 store <16 x i16> %r, ptr %dst, align 32, !nontemporal !11191 ret void1192}1193 1194define void @test_op_v32i8(<32 x i8> %a, <32 x i8> %b, ptr %dst) {1195; SSE-LABEL: test_op_v32i8:1196; SSE: # %bb.0:1197; SSE-NEXT: paddb %xmm2, %xmm01198; SSE-NEXT: paddb %xmm3, %xmm11199; SSE-NEXT: movntdq %xmm1, 16(%rdi)1200; SSE-NEXT: movntdq %xmm0, (%rdi)1201; SSE-NEXT: retq1202;1203; AVX1-LABEL: test_op_v32i8:1204; AVX1: # %bb.0:1205; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm21206; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm11207; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01208; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm01209; AVX1-NEXT: vmovntdq %xmm0, 16(%rdi)1210; AVX1-NEXT: vmovntdq %xmm2, (%rdi)1211; AVX1-NEXT: vzeroupper1212; AVX1-NEXT: retq1213;1214; AVX2-LABEL: test_op_v32i8:1215; AVX2: # %bb.0:1216; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm01217; AVX2-NEXT: vmovntdq %ymm0, (%rdi)1218; AVX2-NEXT: vzeroupper1219; AVX2-NEXT: retq1220;1221; VLX-LABEL: test_op_v32i8:1222; VLX: # %bb.0:1223; VLX-NEXT: vpaddb %ymm1, %ymm0, %ymm01224; VLX-NEXT: vmovntdq %ymm0, (%rdi)1225; VLX-NEXT: vzeroupper1226; VLX-NEXT: retq1227 %r = add <32 x i8> %a, %b1228 store <32 x i8> %r, ptr %dst, align 32, !nontemporal !11229 ret void1230}1231 1232; 256-bit NT stores require 256-bit alignment.1233; For AVX, we lower 128-bit alignment as 2x movntps %xmm.1234define void @test_unaligned_v8f32(<8 x float> %a, <8 x float> %b, ptr %dst) {1235; SSE-LABEL: test_unaligned_v8f32:1236; SSE: # %bb.0:1237; SSE-NEXT: addps %xmm3, %xmm11238; SSE-NEXT: movntps %xmm1, 16(%rdi)1239; SSE-NEXT: addps %xmm2, %xmm01240; SSE-NEXT: movntps %xmm0, (%rdi)1241; SSE-NEXT: retq1242;1243; AVX-LABEL: test_unaligned_v8f32:1244; AVX: # %bb.0:1245; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm01246; AVX-NEXT: vextractf128 $1, %ymm0, %xmm11247; AVX-NEXT: vmovntps %xmm1, 16(%rdi)1248; AVX-NEXT: vmovntps %xmm0, (%rdi)1249; AVX-NEXT: vzeroupper1250; AVX-NEXT: retq1251;1252; VLX-LABEL: test_unaligned_v8f32:1253; VLX: # %bb.0:1254; VLX-NEXT: vaddps %ymm1, %ymm0, %ymm01255; VLX-NEXT: vextractf128 $1, %ymm0, %xmm11256; VLX-NEXT: vmovntps %xmm1, 16(%rdi)1257; VLX-NEXT: vmovntps %xmm0, (%rdi)1258; VLX-NEXT: vzeroupper1259; VLX-NEXT: retq1260 %r = fadd <8 x float> %a, %b1261 store <8 x float> %r, ptr %dst, align 16, !nontemporal !11262 ret void1263}1264 1265!1 = !{i32 1}1266