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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefixes=CHECK,SSE,SSE4A4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE415; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX5128; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX5129 10; Test codegen for under aligned nontemporal vector stores11 12; XMM versions.13 14define void @test_zero_v2f64_align1(ptr %dst) nounwind {15; CHECK-LABEL: test_zero_v2f64_align1:16; CHECK: # %bb.0:17; CHECK-NEXT: xorl %eax, %eax18; CHECK-NEXT: movntiq %rax, 8(%rdi)19; CHECK-NEXT: movntiq %rax, (%rdi)20; CHECK-NEXT: retq21 store <2 x double> zeroinitializer, ptr %dst, align 1, !nontemporal !122 ret void23}24 25define void @test_zero_v4f32_align1(ptr %dst) nounwind {26; CHECK-LABEL: test_zero_v4f32_align1:27; CHECK: # %bb.0:28; CHECK-NEXT: xorl %eax, %eax29; CHECK-NEXT: movntiq %rax, 8(%rdi)30; CHECK-NEXT: movntiq %rax, (%rdi)31; CHECK-NEXT: retq32 store <4 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !133 ret void34}35 36define void @test_zero_v2i64_align1(ptr %dst) nounwind {37; CHECK-LABEL: test_zero_v2i64_align1:38; CHECK: # %bb.0:39; CHECK-NEXT: xorl %eax, %eax40; CHECK-NEXT: movntiq %rax, 8(%rdi)41; CHECK-NEXT: movntiq %rax, (%rdi)42; CHECK-NEXT: retq43 store <2 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !144 ret void45}46 47define void @test_zero_v4i32_align1(ptr %dst) nounwind {48; CHECK-LABEL: test_zero_v4i32_align1:49; CHECK: # %bb.0:50; CHECK-NEXT: xorl %eax, %eax51; CHECK-NEXT: movntiq %rax, 8(%rdi)52; CHECK-NEXT: movntiq %rax, (%rdi)53; CHECK-NEXT: retq54 store <4 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !155 ret void56}57 58define void @test_zero_v8i16_align1(ptr %dst) nounwind {59; CHECK-LABEL: test_zero_v8i16_align1:60; CHECK: # %bb.0:61; CHECK-NEXT: xorl %eax, %eax62; CHECK-NEXT: movntiq %rax, 8(%rdi)63; CHECK-NEXT: movntiq %rax, (%rdi)64; CHECK-NEXT: retq65 store <8 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !166 ret void67}68 69define void @test_zero_v16i8_align1(ptr %dst) nounwind {70; CHECK-LABEL: test_zero_v16i8_align1:71; CHECK: # %bb.0:72; CHECK-NEXT: xorl %eax, %eax73; CHECK-NEXT: movntiq %rax, 8(%rdi)74; CHECK-NEXT: movntiq %rax, (%rdi)75; CHECK-NEXT: retq76 store <16 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !177 ret void78}79 80; YMM versions.81 82define void @test_zero_v4f64_align1(ptr %dst) nounwind {83; CHECK-LABEL: test_zero_v4f64_align1:84; CHECK: # %bb.0:85; CHECK-NEXT: xorl %eax, %eax86; CHECK-NEXT: movntiq %rax, 8(%rdi)87; CHECK-NEXT: movntiq %rax, (%rdi)88; CHECK-NEXT: movntiq %rax, 24(%rdi)89; CHECK-NEXT: movntiq %rax, 16(%rdi)90; CHECK-NEXT: retq91 store <4 x double> zeroinitializer, ptr %dst, align 1, !nontemporal !192 ret void93}94 95define void @test_zero_v8f32_align1(ptr %dst) nounwind {96; CHECK-LABEL: test_zero_v8f32_align1:97; CHECK: # %bb.0:98; CHECK-NEXT: xorl %eax, %eax99; CHECK-NEXT: movntiq %rax, 8(%rdi)100; CHECK-NEXT: movntiq %rax, (%rdi)101; CHECK-NEXT: movntiq %rax, 24(%rdi)102; CHECK-NEXT: movntiq %rax, 16(%rdi)103; CHECK-NEXT: retq104 store <8 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1105 ret void106}107 108define void @test_zero_v4i64_align1(ptr %dst) nounwind {109; CHECK-LABEL: test_zero_v4i64_align1:110; CHECK: # %bb.0:111; CHECK-NEXT: xorl %eax, %eax112; CHECK-NEXT: movntiq %rax, 8(%rdi)113; CHECK-NEXT: movntiq %rax, (%rdi)114; CHECK-NEXT: movntiq %rax, 24(%rdi)115; CHECK-NEXT: movntiq %rax, 16(%rdi)116; CHECK-NEXT: retq117 store <4 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1118 ret void119}120 121define void @test_zero_v8i32_align1(ptr %dst) nounwind {122; CHECK-LABEL: test_zero_v8i32_align1:123; CHECK: # %bb.0:124; CHECK-NEXT: xorl %eax, %eax125; CHECK-NEXT: movntiq %rax, 8(%rdi)126; CHECK-NEXT: movntiq %rax, (%rdi)127; CHECK-NEXT: movntiq %rax, 24(%rdi)128; CHECK-NEXT: movntiq %rax, 16(%rdi)129; CHECK-NEXT: retq130 store <8 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1131 ret void132}133 134define void @test_zero_v16i16_align1(ptr %dst) nounwind {135; CHECK-LABEL: test_zero_v16i16_align1:136; CHECK: # %bb.0:137; CHECK-NEXT: xorl %eax, %eax138; CHECK-NEXT: movntiq %rax, 8(%rdi)139; CHECK-NEXT: movntiq %rax, (%rdi)140; CHECK-NEXT: movntiq %rax, 24(%rdi)141; CHECK-NEXT: movntiq %rax, 16(%rdi)142; CHECK-NEXT: retq143 store <16 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1144 ret void145}146 147define void @test_zero_v32i8_align1(ptr %dst) nounwind {148; CHECK-LABEL: test_zero_v32i8_align1:149; CHECK: # %bb.0:150; CHECK-NEXT: xorl %eax, %eax151; CHECK-NEXT: movntiq %rax, 8(%rdi)152; CHECK-NEXT: movntiq %rax, (%rdi)153; CHECK-NEXT: movntiq %rax, 24(%rdi)154; CHECK-NEXT: movntiq %rax, 16(%rdi)155; CHECK-NEXT: retq156 store <32 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1157 ret void158}159 160define void @test_zero_v4f64_align16(ptr %dst) nounwind {161; SSE-LABEL: test_zero_v4f64_align16:162; SSE: # %bb.0:163; SSE-NEXT: xorps %xmm0, %xmm0164; SSE-NEXT: movntps %xmm0, 16(%rdi)165; SSE-NEXT: movntps %xmm0, (%rdi)166; SSE-NEXT: retq167;168; AVX-LABEL: test_zero_v4f64_align16:169; AVX: # %bb.0:170; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0171; AVX-NEXT: vmovntps %xmm0, 16(%rdi)172; AVX-NEXT: vmovntps %xmm0, (%rdi)173; AVX-NEXT: retq174;175; AVX512-LABEL: test_zero_v4f64_align16:176; AVX512: # %bb.0:177; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0178; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)179; AVX512-NEXT: vmovntps %xmm0, (%rdi)180; AVX512-NEXT: retq181 store <4 x double> zeroinitializer, ptr %dst, align 16, !nontemporal !1182 ret void183}184 185define void @test_zero_v8f32_align16(ptr %dst) nounwind {186; SSE-LABEL: test_zero_v8f32_align16:187; SSE: # %bb.0:188; SSE-NEXT: xorps %xmm0, %xmm0189; SSE-NEXT: movntps %xmm0, 16(%rdi)190; SSE-NEXT: movntps %xmm0, (%rdi)191; SSE-NEXT: retq192;193; AVX-LABEL: test_zero_v8f32_align16:194; AVX: # %bb.0:195; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0196; AVX-NEXT: vmovntps %xmm0, 16(%rdi)197; AVX-NEXT: vmovntps %xmm0, (%rdi)198; AVX-NEXT: retq199;200; AVX512-LABEL: test_zero_v8f32_align16:201; AVX512: # %bb.0:202; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0203; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)204; AVX512-NEXT: vmovntps %xmm0, (%rdi)205; AVX512-NEXT: retq206 store <8 x float> zeroinitializer, ptr %dst, align 16, !nontemporal !1207 ret void208}209 210define void @test_zero_v4i64_align16(ptr %dst) nounwind {211; SSE-LABEL: test_zero_v4i64_align16:212; SSE: # %bb.0:213; SSE-NEXT: xorps %xmm0, %xmm0214; SSE-NEXT: movntps %xmm0, 16(%rdi)215; SSE-NEXT: movntps %xmm0, (%rdi)216; SSE-NEXT: retq217;218; AVX-LABEL: test_zero_v4i64_align16:219; AVX: # %bb.0:220; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0221; AVX-NEXT: vmovntps %xmm0, 16(%rdi)222; AVX-NEXT: vmovntps %xmm0, (%rdi)223; AVX-NEXT: retq224;225; AVX512-LABEL: test_zero_v4i64_align16:226; AVX512: # %bb.0:227; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0228; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)229; AVX512-NEXT: vmovntps %xmm0, (%rdi)230; AVX512-NEXT: retq231 store <4 x i64> zeroinitializer, ptr %dst, align 16, !nontemporal !1232 ret void233}234 235define void @test_zero_v8i32_align16(ptr %dst) nounwind {236; SSE-LABEL: test_zero_v8i32_align16:237; SSE: # %bb.0:238; SSE-NEXT: xorps %xmm0, %xmm0239; SSE-NEXT: movntps %xmm0, 16(%rdi)240; SSE-NEXT: movntps %xmm0, (%rdi)241; SSE-NEXT: retq242;243; AVX-LABEL: test_zero_v8i32_align16:244; AVX: # %bb.0:245; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0246; AVX-NEXT: vmovntps %xmm0, 16(%rdi)247; AVX-NEXT: vmovntps %xmm0, (%rdi)248; AVX-NEXT: retq249;250; AVX512-LABEL: test_zero_v8i32_align16:251; AVX512: # %bb.0:252; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0253; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)254; AVX512-NEXT: vmovntps %xmm0, (%rdi)255; AVX512-NEXT: retq256 store <8 x i32> zeroinitializer, ptr %dst, align 16, !nontemporal !1257 ret void258}259 260define void @test_zero_v16i16_align16(ptr %dst) nounwind {261; SSE-LABEL: test_zero_v16i16_align16:262; SSE: # %bb.0:263; SSE-NEXT: xorps %xmm0, %xmm0264; SSE-NEXT: movntps %xmm0, 16(%rdi)265; SSE-NEXT: movntps %xmm0, (%rdi)266; SSE-NEXT: retq267;268; AVX-LABEL: test_zero_v16i16_align16:269; AVX: # %bb.0:270; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0271; AVX-NEXT: vmovntps %xmm0, 16(%rdi)272; AVX-NEXT: vmovntps %xmm0, (%rdi)273; AVX-NEXT: retq274;275; AVX512-LABEL: test_zero_v16i16_align16:276; AVX512: # %bb.0:277; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0278; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)279; AVX512-NEXT: vmovntps %xmm0, (%rdi)280; AVX512-NEXT: retq281 store <16 x i16> zeroinitializer, ptr %dst, align 16, !nontemporal !1282 ret void283}284 285define void @test_zero_v32i8_align16(ptr %dst) nounwind {286; SSE-LABEL: test_zero_v32i8_align16:287; SSE: # %bb.0:288; SSE-NEXT: xorps %xmm0, %xmm0289; SSE-NEXT: movntps %xmm0, 16(%rdi)290; SSE-NEXT: movntps %xmm0, (%rdi)291; SSE-NEXT: retq292;293; AVX-LABEL: test_zero_v32i8_align16:294; AVX: # %bb.0:295; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0296; AVX-NEXT: vmovntps %xmm0, 16(%rdi)297; AVX-NEXT: vmovntps %xmm0, (%rdi)298; AVX-NEXT: retq299;300; AVX512-LABEL: test_zero_v32i8_align16:301; AVX512: # %bb.0:302; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0303; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)304; AVX512-NEXT: vmovntps %xmm0, (%rdi)305; AVX512-NEXT: retq306 store <32 x i8> zeroinitializer, ptr %dst, align 16, !nontemporal !1307 ret void308}309 310; ZMM versions.311 312define void @test_zero_v8f64_align1(ptr %dst) nounwind {313; CHECK-LABEL: test_zero_v8f64_align1:314; CHECK: # %bb.0:315; CHECK-NEXT: xorl %eax, %eax316; CHECK-NEXT: movntiq %rax, 8(%rdi)317; CHECK-NEXT: movntiq %rax, (%rdi)318; CHECK-NEXT: movntiq %rax, 24(%rdi)319; CHECK-NEXT: movntiq %rax, 16(%rdi)320; CHECK-NEXT: movntiq %rax, 40(%rdi)321; CHECK-NEXT: movntiq %rax, 32(%rdi)322; CHECK-NEXT: movntiq %rax, 56(%rdi)323; CHECK-NEXT: movntiq %rax, 48(%rdi)324; CHECK-NEXT: retq325 store <8 x double> zeroinitializer, ptr %dst, align 1, !nontemporal !1326 ret void327}328 329define void @test_zero_v16f32_align1(ptr %dst) nounwind {330; CHECK-LABEL: test_zero_v16f32_align1:331; CHECK: # %bb.0:332; CHECK-NEXT: xorl %eax, %eax333; CHECK-NEXT: movntiq %rax, 8(%rdi)334; CHECK-NEXT: movntiq %rax, (%rdi)335; CHECK-NEXT: movntiq %rax, 24(%rdi)336; CHECK-NEXT: movntiq %rax, 16(%rdi)337; CHECK-NEXT: movntiq %rax, 40(%rdi)338; CHECK-NEXT: movntiq %rax, 32(%rdi)339; CHECK-NEXT: movntiq %rax, 56(%rdi)340; CHECK-NEXT: movntiq %rax, 48(%rdi)341; CHECK-NEXT: retq342 store <16 x float> zeroinitializer, ptr %dst, align 1, !nontemporal !1343 ret void344}345 346define void @test_zero_v8i64_align1(ptr %dst) nounwind {347; CHECK-LABEL: test_zero_v8i64_align1:348; CHECK: # %bb.0:349; CHECK-NEXT: xorl %eax, %eax350; CHECK-NEXT: movntiq %rax, 8(%rdi)351; CHECK-NEXT: movntiq %rax, (%rdi)352; CHECK-NEXT: movntiq %rax, 24(%rdi)353; CHECK-NEXT: movntiq %rax, 16(%rdi)354; CHECK-NEXT: movntiq %rax, 40(%rdi)355; CHECK-NEXT: movntiq %rax, 32(%rdi)356; CHECK-NEXT: movntiq %rax, 56(%rdi)357; CHECK-NEXT: movntiq %rax, 48(%rdi)358; CHECK-NEXT: retq359 store <8 x i64> zeroinitializer, ptr %dst, align 1, !nontemporal !1360 ret void361}362 363define void @test_zero_v16i32_align1(ptr %dst) nounwind {364; CHECK-LABEL: test_zero_v16i32_align1:365; CHECK: # %bb.0:366; CHECK-NEXT: xorl %eax, %eax367; CHECK-NEXT: movntiq %rax, 8(%rdi)368; CHECK-NEXT: movntiq %rax, (%rdi)369; CHECK-NEXT: movntiq %rax, 24(%rdi)370; CHECK-NEXT: movntiq %rax, 16(%rdi)371; CHECK-NEXT: movntiq %rax, 40(%rdi)372; CHECK-NEXT: movntiq %rax, 32(%rdi)373; CHECK-NEXT: movntiq %rax, 56(%rdi)374; CHECK-NEXT: movntiq %rax, 48(%rdi)375; CHECK-NEXT: retq376 store <16 x i32> zeroinitializer, ptr %dst, align 1, !nontemporal !1377 ret void378}379 380define void @test_zero_v32i16_align1(ptr %dst) nounwind {381; CHECK-LABEL: test_zero_v32i16_align1:382; CHECK: # %bb.0:383; CHECK-NEXT: xorl %eax, %eax384; CHECK-NEXT: movntiq %rax, 8(%rdi)385; CHECK-NEXT: movntiq %rax, (%rdi)386; CHECK-NEXT: movntiq %rax, 24(%rdi)387; CHECK-NEXT: movntiq %rax, 16(%rdi)388; CHECK-NEXT: movntiq %rax, 40(%rdi)389; CHECK-NEXT: movntiq %rax, 32(%rdi)390; CHECK-NEXT: movntiq %rax, 56(%rdi)391; CHECK-NEXT: movntiq %rax, 48(%rdi)392; CHECK-NEXT: retq393 store <32 x i16> zeroinitializer, ptr %dst, align 1, !nontemporal !1394 ret void395}396 397define void @test_zero_v64i8_align1(ptr %dst) nounwind {398; CHECK-LABEL: test_zero_v64i8_align1:399; CHECK: # %bb.0:400; CHECK-NEXT: xorl %eax, %eax401; CHECK-NEXT: movntiq %rax, 8(%rdi)402; CHECK-NEXT: movntiq %rax, (%rdi)403; CHECK-NEXT: movntiq %rax, 24(%rdi)404; CHECK-NEXT: movntiq %rax, 16(%rdi)405; CHECK-NEXT: movntiq %rax, 40(%rdi)406; CHECK-NEXT: movntiq %rax, 32(%rdi)407; CHECK-NEXT: movntiq %rax, 56(%rdi)408; CHECK-NEXT: movntiq %rax, 48(%rdi)409; CHECK-NEXT: retq410 store <64 x i8> zeroinitializer, ptr %dst, align 1, !nontemporal !1411 ret void412}413 414define void @test_zero_v8f64_align16(ptr %dst) nounwind {415; SSE-LABEL: test_zero_v8f64_align16:416; SSE: # %bb.0:417; SSE-NEXT: xorps %xmm0, %xmm0418; SSE-NEXT: movntps %xmm0, 16(%rdi)419; SSE-NEXT: movntps %xmm0, (%rdi)420; SSE-NEXT: movntps %xmm0, 48(%rdi)421; SSE-NEXT: movntps %xmm0, 32(%rdi)422; SSE-NEXT: retq423;424; AVX-LABEL: test_zero_v8f64_align16:425; AVX: # %bb.0:426; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0427; AVX-NEXT: vmovntps %xmm0, 16(%rdi)428; AVX-NEXT: vmovntps %xmm0, (%rdi)429; AVX-NEXT: vmovntps %xmm0, 48(%rdi)430; AVX-NEXT: vmovntps %xmm0, 32(%rdi)431; AVX-NEXT: retq432;433; AVX512-LABEL: test_zero_v8f64_align16:434; AVX512: # %bb.0:435; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0436; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)437; AVX512-NEXT: vmovntps %xmm0, (%rdi)438; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)439; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)440; AVX512-NEXT: retq441 store <8 x double> zeroinitializer, ptr %dst, align 16, !nontemporal !1442 ret void443}444 445define void @test_zero_v16f32_align16(ptr %dst) nounwind {446; SSE-LABEL: test_zero_v16f32_align16:447; SSE: # %bb.0:448; SSE-NEXT: xorps %xmm0, %xmm0449; SSE-NEXT: movntps %xmm0, 16(%rdi)450; SSE-NEXT: movntps %xmm0, (%rdi)451; SSE-NEXT: movntps %xmm0, 48(%rdi)452; SSE-NEXT: movntps %xmm0, 32(%rdi)453; SSE-NEXT: retq454;455; AVX-LABEL: test_zero_v16f32_align16:456; AVX: # %bb.0:457; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0458; AVX-NEXT: vmovntps %xmm0, 16(%rdi)459; AVX-NEXT: vmovntps %xmm0, (%rdi)460; AVX-NEXT: vmovntps %xmm0, 48(%rdi)461; AVX-NEXT: vmovntps %xmm0, 32(%rdi)462; AVX-NEXT: retq463;464; AVX512-LABEL: test_zero_v16f32_align16:465; AVX512: # %bb.0:466; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0467; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)468; AVX512-NEXT: vmovntps %xmm0, (%rdi)469; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)470; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)471; AVX512-NEXT: retq472 store <16 x float> zeroinitializer, ptr %dst, align 16, !nontemporal !1473 ret void474}475 476define void @test_zero_v8i64_align16(ptr %dst) nounwind {477; SSE-LABEL: test_zero_v8i64_align16:478; SSE: # %bb.0:479; SSE-NEXT: xorps %xmm0, %xmm0480; SSE-NEXT: movntps %xmm0, 16(%rdi)481; SSE-NEXT: movntps %xmm0, (%rdi)482; SSE-NEXT: movntps %xmm0, 48(%rdi)483; SSE-NEXT: movntps %xmm0, 32(%rdi)484; SSE-NEXT: retq485;486; AVX-LABEL: test_zero_v8i64_align16:487; AVX: # %bb.0:488; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0489; AVX-NEXT: vmovntps %xmm0, 16(%rdi)490; AVX-NEXT: vmovntps %xmm0, (%rdi)491; AVX-NEXT: vmovntps %xmm0, 48(%rdi)492; AVX-NEXT: vmovntps %xmm0, 32(%rdi)493; AVX-NEXT: retq494;495; AVX512-LABEL: test_zero_v8i64_align16:496; AVX512: # %bb.0:497; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0498; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)499; AVX512-NEXT: vmovntps %xmm0, (%rdi)500; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)501; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)502; AVX512-NEXT: retq503 store <8 x i64> zeroinitializer, ptr %dst, align 16, !nontemporal !1504 ret void505}506 507define void @test_zero_v16i32_align16(ptr %dst) nounwind {508; SSE-LABEL: test_zero_v16i32_align16:509; SSE: # %bb.0:510; SSE-NEXT: xorps %xmm0, %xmm0511; SSE-NEXT: movntps %xmm0, 16(%rdi)512; SSE-NEXT: movntps %xmm0, (%rdi)513; SSE-NEXT: movntps %xmm0, 48(%rdi)514; SSE-NEXT: movntps %xmm0, 32(%rdi)515; SSE-NEXT: retq516;517; AVX-LABEL: test_zero_v16i32_align16:518; AVX: # %bb.0:519; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0520; AVX-NEXT: vmovntps %xmm0, 16(%rdi)521; AVX-NEXT: vmovntps %xmm0, (%rdi)522; AVX-NEXT: vmovntps %xmm0, 48(%rdi)523; AVX-NEXT: vmovntps %xmm0, 32(%rdi)524; AVX-NEXT: retq525;526; AVX512-LABEL: test_zero_v16i32_align16:527; AVX512: # %bb.0:528; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0529; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)530; AVX512-NEXT: vmovntps %xmm0, (%rdi)531; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)532; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)533; AVX512-NEXT: retq534 store <16 x i32> zeroinitializer, ptr %dst, align 16, !nontemporal !1535 ret void536}537 538define void @test_zero_v32i16_align16(ptr %dst) nounwind {539; SSE-LABEL: test_zero_v32i16_align16:540; SSE: # %bb.0:541; SSE-NEXT: xorps %xmm0, %xmm0542; SSE-NEXT: movntps %xmm0, 16(%rdi)543; SSE-NEXT: movntps %xmm0, (%rdi)544; SSE-NEXT: movntps %xmm0, 48(%rdi)545; SSE-NEXT: movntps %xmm0, 32(%rdi)546; SSE-NEXT: retq547;548; AVX-LABEL: test_zero_v32i16_align16:549; AVX: # %bb.0:550; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0551; AVX-NEXT: vmovntps %xmm0, 16(%rdi)552; AVX-NEXT: vmovntps %xmm0, (%rdi)553; AVX-NEXT: vmovntps %xmm0, 48(%rdi)554; AVX-NEXT: vmovntps %xmm0, 32(%rdi)555; AVX-NEXT: retq556;557; AVX512-LABEL: test_zero_v32i16_align16:558; AVX512: # %bb.0:559; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0560; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)561; AVX512-NEXT: vmovntps %xmm0, (%rdi)562; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)563; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)564; AVX512-NEXT: retq565 store <32 x i16> zeroinitializer, ptr %dst, align 16, !nontemporal !1566 ret void567}568 569define void @test_zero_v64i8_align16(ptr %dst) nounwind {570; SSE-LABEL: test_zero_v64i8_align16:571; SSE: # %bb.0:572; SSE-NEXT: xorps %xmm0, %xmm0573; SSE-NEXT: movntps %xmm0, 16(%rdi)574; SSE-NEXT: movntps %xmm0, (%rdi)575; SSE-NEXT: movntps %xmm0, 48(%rdi)576; SSE-NEXT: movntps %xmm0, 32(%rdi)577; SSE-NEXT: retq578;579; AVX-LABEL: test_zero_v64i8_align16:580; AVX: # %bb.0:581; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0582; AVX-NEXT: vmovntps %xmm0, 16(%rdi)583; AVX-NEXT: vmovntps %xmm0, (%rdi)584; AVX-NEXT: vmovntps %xmm0, 48(%rdi)585; AVX-NEXT: vmovntps %xmm0, 32(%rdi)586; AVX-NEXT: retq587;588; AVX512-LABEL: test_zero_v64i8_align16:589; AVX512: # %bb.0:590; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0591; AVX512-NEXT: vmovntps %xmm0, 16(%rdi)592; AVX512-NEXT: vmovntps %xmm0, (%rdi)593; AVX512-NEXT: vmovntps %xmm0, 48(%rdi)594; AVX512-NEXT: vmovntps %xmm0, 32(%rdi)595; AVX512-NEXT: retq596 store <64 x i8> zeroinitializer, ptr %dst, align 16, !nontemporal !1597 ret void598}599 600define void @test_zero_v8f64_align32(ptr %dst) nounwind {601; SSE-LABEL: test_zero_v8f64_align32:602; SSE: # %bb.0:603; SSE-NEXT: xorps %xmm0, %xmm0604; SSE-NEXT: movntps %xmm0, 48(%rdi)605; SSE-NEXT: movntps %xmm0, 32(%rdi)606; SSE-NEXT: movntps %xmm0, 16(%rdi)607; SSE-NEXT: movntps %xmm0, (%rdi)608; SSE-NEXT: retq609;610; AVX-LABEL: test_zero_v8f64_align32:611; AVX: # %bb.0:612; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0613; AVX-NEXT: vmovntps %ymm0, 32(%rdi)614; AVX-NEXT: vmovntps %ymm0, (%rdi)615; AVX-NEXT: vzeroupper616; AVX-NEXT: retq617;618; AVX512-LABEL: test_zero_v8f64_align32:619; AVX512: # %bb.0:620; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0621; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)622; AVX512-NEXT: vmovntps %ymm0, (%rdi)623; AVX512-NEXT: vzeroupper624; AVX512-NEXT: retq625 store <8 x double> zeroinitializer, ptr %dst, align 32, !nontemporal !1626 ret void627}628 629define void @test_zero_v16f32_align32(ptr %dst) nounwind {630; SSE-LABEL: test_zero_v16f32_align32:631; SSE: # %bb.0:632; SSE-NEXT: xorps %xmm0, %xmm0633; SSE-NEXT: movntps %xmm0, 48(%rdi)634; SSE-NEXT: movntps %xmm0, 32(%rdi)635; SSE-NEXT: movntps %xmm0, 16(%rdi)636; SSE-NEXT: movntps %xmm0, (%rdi)637; SSE-NEXT: retq638;639; AVX-LABEL: test_zero_v16f32_align32:640; AVX: # %bb.0:641; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0642; AVX-NEXT: vmovntps %ymm0, 32(%rdi)643; AVX-NEXT: vmovntps %ymm0, (%rdi)644; AVX-NEXT: vzeroupper645; AVX-NEXT: retq646;647; AVX512-LABEL: test_zero_v16f32_align32:648; AVX512: # %bb.0:649; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0650; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)651; AVX512-NEXT: vmovntps %ymm0, (%rdi)652; AVX512-NEXT: vzeroupper653; AVX512-NEXT: retq654 store <16 x float> zeroinitializer, ptr %dst, align 32, !nontemporal !1655 ret void656}657 658define void @test_zero_v8i64_align32(ptr %dst) nounwind {659; SSE-LABEL: test_zero_v8i64_align32:660; SSE: # %bb.0:661; SSE-NEXT: xorps %xmm0, %xmm0662; SSE-NEXT: movntps %xmm0, 48(%rdi)663; SSE-NEXT: movntps %xmm0, 32(%rdi)664; SSE-NEXT: movntps %xmm0, 16(%rdi)665; SSE-NEXT: movntps %xmm0, (%rdi)666; SSE-NEXT: retq667;668; AVX-LABEL: test_zero_v8i64_align32:669; AVX: # %bb.0:670; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0671; AVX-NEXT: vmovntps %ymm0, 32(%rdi)672; AVX-NEXT: vmovntps %ymm0, (%rdi)673; AVX-NEXT: vzeroupper674; AVX-NEXT: retq675;676; AVX512-LABEL: test_zero_v8i64_align32:677; AVX512: # %bb.0:678; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0679; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)680; AVX512-NEXT: vmovntps %ymm0, (%rdi)681; AVX512-NEXT: vzeroupper682; AVX512-NEXT: retq683 store <8 x i64> zeroinitializer, ptr %dst, align 32, !nontemporal !1684 ret void685}686 687define void @test_zero_v16i32_align32(ptr %dst) nounwind {688; SSE-LABEL: test_zero_v16i32_align32:689; SSE: # %bb.0:690; SSE-NEXT: xorps %xmm0, %xmm0691; SSE-NEXT: movntps %xmm0, 48(%rdi)692; SSE-NEXT: movntps %xmm0, 32(%rdi)693; SSE-NEXT: movntps %xmm0, 16(%rdi)694; SSE-NEXT: movntps %xmm0, (%rdi)695; SSE-NEXT: retq696;697; AVX-LABEL: test_zero_v16i32_align32:698; AVX: # %bb.0:699; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0700; AVX-NEXT: vmovntps %ymm0, 32(%rdi)701; AVX-NEXT: vmovntps %ymm0, (%rdi)702; AVX-NEXT: vzeroupper703; AVX-NEXT: retq704;705; AVX512-LABEL: test_zero_v16i32_align32:706; AVX512: # %bb.0:707; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0708; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)709; AVX512-NEXT: vmovntps %ymm0, (%rdi)710; AVX512-NEXT: vzeroupper711; AVX512-NEXT: retq712 store <16 x i32> zeroinitializer, ptr %dst, align 32, !nontemporal !1713 ret void714}715 716define void @test_zero_v32i16_align32(ptr %dst) nounwind {717; SSE-LABEL: test_zero_v32i16_align32:718; SSE: # %bb.0:719; SSE-NEXT: xorps %xmm0, %xmm0720; SSE-NEXT: movntps %xmm0, 48(%rdi)721; SSE-NEXT: movntps %xmm0, 32(%rdi)722; SSE-NEXT: movntps %xmm0, 16(%rdi)723; SSE-NEXT: movntps %xmm0, (%rdi)724; SSE-NEXT: retq725;726; AVX-LABEL: test_zero_v32i16_align32:727; AVX: # %bb.0:728; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0729; AVX-NEXT: vmovntps %ymm0, 32(%rdi)730; AVX-NEXT: vmovntps %ymm0, (%rdi)731; AVX-NEXT: vzeroupper732; AVX-NEXT: retq733;734; AVX512-LABEL: test_zero_v32i16_align32:735; AVX512: # %bb.0:736; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0737; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)738; AVX512-NEXT: vmovntps %ymm0, (%rdi)739; AVX512-NEXT: vzeroupper740; AVX512-NEXT: retq741 store <32 x i16> zeroinitializer, ptr %dst, align 32, !nontemporal !1742 ret void743}744 745define void @test_zero_v64i8_align32(ptr %dst) nounwind {746; SSE-LABEL: test_zero_v64i8_align32:747; SSE: # %bb.0:748; SSE-NEXT: xorps %xmm0, %xmm0749; SSE-NEXT: movntps %xmm0, 48(%rdi)750; SSE-NEXT: movntps %xmm0, 32(%rdi)751; SSE-NEXT: movntps %xmm0, 16(%rdi)752; SSE-NEXT: movntps %xmm0, (%rdi)753; SSE-NEXT: retq754;755; AVX-LABEL: test_zero_v64i8_align32:756; AVX: # %bb.0:757; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0758; AVX-NEXT: vmovntps %ymm0, 32(%rdi)759; AVX-NEXT: vmovntps %ymm0, (%rdi)760; AVX-NEXT: vzeroupper761; AVX-NEXT: retq762;763; AVX512-LABEL: test_zero_v64i8_align32:764; AVX512: # %bb.0:765; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0766; AVX512-NEXT: vmovntps %ymm0, 32(%rdi)767; AVX512-NEXT: vmovntps %ymm0, (%rdi)768; AVX512-NEXT: vzeroupper769; AVX512-NEXT: retq770 store <64 x i8> zeroinitializer, ptr %dst, align 32, !nontemporal !1771 ret void772}773 774!1 = !{i32 1}775;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:776; SSE2: {{.*}}777; SSE41: {{.*}}778; SSE4A: {{.*}}779