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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX15; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX5127; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX5128 9; Test codegen for under aligned nontemporal vector loads10 11; XMM versions.12 13define <2 x double> @test_v2f64_align1(ptr %src) nounwind {14; SSE-LABEL: test_v2f64_align1:15; SSE: # %bb.0:16; SSE-NEXT: movups (%rdi), %xmm017; SSE-NEXT: retq18;19; AVX-LABEL: test_v2f64_align1:20; AVX: # %bb.0:21; AVX-NEXT: vmovups (%rdi), %xmm022; AVX-NEXT: retq23 %1 = load <2 x double>, ptr %src, align 1, !nontemporal !124 ret <2 x double> %125}26 27define <4 x float> @test_v4f32_align1(ptr %src) nounwind {28; SSE-LABEL: test_v4f32_align1:29; SSE: # %bb.0:30; SSE-NEXT: movups (%rdi), %xmm031; SSE-NEXT: retq32;33; AVX-LABEL: test_v4f32_align1:34; AVX: # %bb.0:35; AVX-NEXT: vmovups (%rdi), %xmm036; AVX-NEXT: retq37 %1 = load <4 x float>, ptr %src, align 1, !nontemporal !138 ret <4 x float> %139}40 41define <2 x i64> @test_v2i64_align1(ptr %src) nounwind {42; SSE-LABEL: test_v2i64_align1:43; SSE: # %bb.0:44; SSE-NEXT: movups (%rdi), %xmm045; SSE-NEXT: retq46;47; AVX-LABEL: test_v2i64_align1:48; AVX: # %bb.0:49; AVX-NEXT: vmovups (%rdi), %xmm050; AVX-NEXT: retq51 %1 = load <2 x i64>, ptr %src, align 1, !nontemporal !152 ret <2 x i64> %153}54 55define <4 x i32> @test_v4i32_align1(ptr %src) nounwind {56; SSE-LABEL: test_v4i32_align1:57; SSE: # %bb.0:58; SSE-NEXT: movups (%rdi), %xmm059; SSE-NEXT: retq60;61; AVX-LABEL: test_v4i32_align1:62; AVX: # %bb.0:63; AVX-NEXT: vmovups (%rdi), %xmm064; AVX-NEXT: retq65 %1 = load <4 x i32>, ptr %src, align 1, !nontemporal !166 ret <4 x i32> %167}68 69define <8 x i16> @test_v8i16_align1(ptr %src) nounwind {70; SSE-LABEL: test_v8i16_align1:71; SSE: # %bb.0:72; SSE-NEXT: movups (%rdi), %xmm073; SSE-NEXT: retq74;75; AVX-LABEL: test_v8i16_align1:76; AVX: # %bb.0:77; AVX-NEXT: vmovups (%rdi), %xmm078; AVX-NEXT: retq79 %1 = load <8 x i16>, ptr %src, align 1, !nontemporal !180 ret <8 x i16> %181}82 83define <16 x i8> @test_v16i8_align1(ptr %src) nounwind {84; SSE-LABEL: test_v16i8_align1:85; SSE: # %bb.0:86; SSE-NEXT: movups (%rdi), %xmm087; SSE-NEXT: retq88;89; AVX-LABEL: test_v16i8_align1:90; AVX: # %bb.0:91; AVX-NEXT: vmovups (%rdi), %xmm092; AVX-NEXT: retq93 %1 = load <16 x i8>, ptr %src, align 1, !nontemporal !194 ret <16 x i8> %195}96 97; YMM versions.98 99define <4 x double> @test_v4f64_align1(ptr %src) nounwind {100; SSE-LABEL: test_v4f64_align1:101; SSE: # %bb.0:102; SSE-NEXT: movups (%rdi), %xmm0103; SSE-NEXT: movups 16(%rdi), %xmm1104; SSE-NEXT: retq105;106; AVX-LABEL: test_v4f64_align1:107; AVX: # %bb.0:108; AVX-NEXT: vmovups (%rdi), %ymm0109; AVX-NEXT: retq110 %1 = load <4 x double>, ptr %src, align 1, !nontemporal !1111 ret <4 x double> %1112}113 114define <8 x float> @test_v8f32_align1(ptr %src) nounwind {115; SSE-LABEL: test_v8f32_align1:116; SSE: # %bb.0:117; SSE-NEXT: movups (%rdi), %xmm0118; SSE-NEXT: movups 16(%rdi), %xmm1119; SSE-NEXT: retq120;121; AVX-LABEL: test_v8f32_align1:122; AVX: # %bb.0:123; AVX-NEXT: vmovups (%rdi), %ymm0124; AVX-NEXT: retq125 %1 = load <8 x float>, ptr %src, align 1, !nontemporal !1126 ret <8 x float> %1127}128 129define <4 x i64> @test_v4i64_align1(ptr %src) nounwind {130; SSE-LABEL: test_v4i64_align1:131; SSE: # %bb.0:132; SSE-NEXT: movups (%rdi), %xmm0133; SSE-NEXT: movups 16(%rdi), %xmm1134; SSE-NEXT: retq135;136; AVX-LABEL: test_v4i64_align1:137; AVX: # %bb.0:138; AVX-NEXT: vmovups (%rdi), %ymm0139; AVX-NEXT: retq140 %1 = load <4 x i64>, ptr %src, align 1, !nontemporal !1141 ret <4 x i64> %1142}143 144define <8 x i32> @test_v8i32_align1(ptr %src) nounwind {145; SSE-LABEL: test_v8i32_align1:146; SSE: # %bb.0:147; SSE-NEXT: movups (%rdi), %xmm0148; SSE-NEXT: movups 16(%rdi), %xmm1149; SSE-NEXT: retq150;151; AVX-LABEL: test_v8i32_align1:152; AVX: # %bb.0:153; AVX-NEXT: vmovups (%rdi), %ymm0154; AVX-NEXT: retq155 %1 = load <8 x i32>, ptr %src, align 1, !nontemporal !1156 ret <8 x i32> %1157}158 159define <16 x i16> @test_v16i16_align1(ptr %src) nounwind {160; SSE-LABEL: test_v16i16_align1:161; SSE: # %bb.0:162; SSE-NEXT: movups (%rdi), %xmm0163; SSE-NEXT: movups 16(%rdi), %xmm1164; SSE-NEXT: retq165;166; AVX-LABEL: test_v16i16_align1:167; AVX: # %bb.0:168; AVX-NEXT: vmovups (%rdi), %ymm0169; AVX-NEXT: retq170 %1 = load <16 x i16>, ptr %src, align 1, !nontemporal !1171 ret <16 x i16> %1172}173 174define <32 x i8> @test_v32i8_align1(ptr %src) nounwind {175; SSE-LABEL: test_v32i8_align1:176; SSE: # %bb.0:177; SSE-NEXT: movups (%rdi), %xmm0178; SSE-NEXT: movups 16(%rdi), %xmm1179; SSE-NEXT: retq180;181; AVX-LABEL: test_v32i8_align1:182; AVX: # %bb.0:183; AVX-NEXT: vmovups (%rdi), %ymm0184; AVX-NEXT: retq185 %1 = load <32 x i8>, ptr %src, align 1, !nontemporal !1186 ret <32 x i8> %1187}188 189define <4 x double> @test_v4f64_align16(ptr %src) nounwind {190; SSE2-LABEL: test_v4f64_align16:191; SSE2: # %bb.0:192; SSE2-NEXT: movaps (%rdi), %xmm0193; SSE2-NEXT: movaps 16(%rdi), %xmm1194; SSE2-NEXT: retq195;196; SSE41-LABEL: test_v4f64_align16:197; SSE41: # %bb.0:198; SSE41-NEXT: movntdqa (%rdi), %xmm0199; SSE41-NEXT: movntdqa 16(%rdi), %xmm1200; SSE41-NEXT: retq201;202; AVX-LABEL: test_v4f64_align16:203; AVX: # %bb.0:204; AVX-NEXT: pushq %rbp205; AVX-NEXT: movq %rsp, %rbp206; AVX-NEXT: andq $-32, %rsp207; AVX-NEXT: subq $64, %rsp208; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0209; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)210; AVX-NEXT: vmovntdqa (%rdi), %xmm0211; AVX-NEXT: vmovdqa %xmm0, (%rsp)212; AVX-NEXT: vmovaps (%rsp), %ymm0213; AVX-NEXT: movq %rbp, %rsp214; AVX-NEXT: popq %rbp215; AVX-NEXT: retq216 %1 = load <4 x double>, ptr %src, align 16, !nontemporal !1217 ret <4 x double> %1218}219 220define <8 x float> @test_v8f32_align16(ptr %src) nounwind {221; SSE2-LABEL: test_v8f32_align16:222; SSE2: # %bb.0:223; SSE2-NEXT: movaps (%rdi), %xmm0224; SSE2-NEXT: movaps 16(%rdi), %xmm1225; SSE2-NEXT: retq226;227; SSE41-LABEL: test_v8f32_align16:228; SSE41: # %bb.0:229; SSE41-NEXT: movntdqa (%rdi), %xmm0230; SSE41-NEXT: movntdqa 16(%rdi), %xmm1231; SSE41-NEXT: retq232;233; AVX-LABEL: test_v8f32_align16:234; AVX: # %bb.0:235; AVX-NEXT: pushq %rbp236; AVX-NEXT: movq %rsp, %rbp237; AVX-NEXT: andq $-32, %rsp238; AVX-NEXT: subq $64, %rsp239; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0240; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)241; AVX-NEXT: vmovntdqa (%rdi), %xmm0242; AVX-NEXT: vmovdqa %xmm0, (%rsp)243; AVX-NEXT: vmovaps (%rsp), %ymm0244; AVX-NEXT: movq %rbp, %rsp245; AVX-NEXT: popq %rbp246; AVX-NEXT: retq247 %1 = load <8 x float>, ptr %src, align 16, !nontemporal !1248 ret <8 x float> %1249}250 251define <4 x i64> @test_v4i64_align16(ptr %src) nounwind {252; SSE2-LABEL: test_v4i64_align16:253; SSE2: # %bb.0:254; SSE2-NEXT: movaps (%rdi), %xmm0255; SSE2-NEXT: movaps 16(%rdi), %xmm1256; SSE2-NEXT: retq257;258; SSE41-LABEL: test_v4i64_align16:259; SSE41: # %bb.0:260; SSE41-NEXT: movntdqa (%rdi), %xmm0261; SSE41-NEXT: movntdqa 16(%rdi), %xmm1262; SSE41-NEXT: retq263;264; AVX-LABEL: test_v4i64_align16:265; AVX: # %bb.0:266; AVX-NEXT: pushq %rbp267; AVX-NEXT: movq %rsp, %rbp268; AVX-NEXT: andq $-32, %rsp269; AVX-NEXT: subq $64, %rsp270; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0271; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)272; AVX-NEXT: vmovntdqa (%rdi), %xmm0273; AVX-NEXT: vmovdqa %xmm0, (%rsp)274; AVX-NEXT: vmovaps (%rsp), %ymm0275; AVX-NEXT: movq %rbp, %rsp276; AVX-NEXT: popq %rbp277; AVX-NEXT: retq278 %1 = load <4 x i64>, ptr %src, align 16, !nontemporal !1279 ret <4 x i64> %1280}281 282define <8 x i32> @test_v8i32_align16(ptr %src) nounwind {283; SSE2-LABEL: test_v8i32_align16:284; SSE2: # %bb.0:285; SSE2-NEXT: movaps (%rdi), %xmm0286; SSE2-NEXT: movaps 16(%rdi), %xmm1287; SSE2-NEXT: retq288;289; SSE41-LABEL: test_v8i32_align16:290; SSE41: # %bb.0:291; SSE41-NEXT: movntdqa (%rdi), %xmm0292; SSE41-NEXT: movntdqa 16(%rdi), %xmm1293; SSE41-NEXT: retq294;295; AVX-LABEL: test_v8i32_align16:296; AVX: # %bb.0:297; AVX-NEXT: pushq %rbp298; AVX-NEXT: movq %rsp, %rbp299; AVX-NEXT: andq $-32, %rsp300; AVX-NEXT: subq $64, %rsp301; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0302; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)303; AVX-NEXT: vmovntdqa (%rdi), %xmm0304; AVX-NEXT: vmovdqa %xmm0, (%rsp)305; AVX-NEXT: vmovaps (%rsp), %ymm0306; AVX-NEXT: movq %rbp, %rsp307; AVX-NEXT: popq %rbp308; AVX-NEXT: retq309 %1 = load <8 x i32>, ptr %src, align 16, !nontemporal !1310 ret <8 x i32> %1311}312 313define <16 x i16> @test_v16i16_align16(ptr %src) nounwind {314; SSE2-LABEL: test_v16i16_align16:315; SSE2: # %bb.0:316; SSE2-NEXT: movaps (%rdi), %xmm0317; SSE2-NEXT: movaps 16(%rdi), %xmm1318; SSE2-NEXT: retq319;320; SSE41-LABEL: test_v16i16_align16:321; SSE41: # %bb.0:322; SSE41-NEXT: movntdqa (%rdi), %xmm0323; SSE41-NEXT: movntdqa 16(%rdi), %xmm1324; SSE41-NEXT: retq325;326; AVX-LABEL: test_v16i16_align16:327; AVX: # %bb.0:328; AVX-NEXT: pushq %rbp329; AVX-NEXT: movq %rsp, %rbp330; AVX-NEXT: andq $-32, %rsp331; AVX-NEXT: subq $64, %rsp332; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0333; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)334; AVX-NEXT: vmovntdqa (%rdi), %xmm0335; AVX-NEXT: vmovdqa %xmm0, (%rsp)336; AVX-NEXT: vmovaps (%rsp), %ymm0337; AVX-NEXT: movq %rbp, %rsp338; AVX-NEXT: popq %rbp339; AVX-NEXT: retq340 %1 = load <16 x i16>, ptr %src, align 16, !nontemporal !1341 ret <16 x i16> %1342}343 344define <32 x i8> @test_v32i8_align16(ptr %src) nounwind {345; SSE2-LABEL: test_v32i8_align16:346; SSE2: # %bb.0:347; SSE2-NEXT: movaps (%rdi), %xmm0348; SSE2-NEXT: movaps 16(%rdi), %xmm1349; SSE2-NEXT: retq350;351; SSE41-LABEL: test_v32i8_align16:352; SSE41: # %bb.0:353; SSE41-NEXT: movntdqa (%rdi), %xmm0354; SSE41-NEXT: movntdqa 16(%rdi), %xmm1355; SSE41-NEXT: retq356;357; AVX-LABEL: test_v32i8_align16:358; AVX: # %bb.0:359; AVX-NEXT: pushq %rbp360; AVX-NEXT: movq %rsp, %rbp361; AVX-NEXT: andq $-32, %rsp362; AVX-NEXT: subq $64, %rsp363; AVX-NEXT: vmovntdqa 16(%rdi), %xmm0364; AVX-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)365; AVX-NEXT: vmovntdqa (%rdi), %xmm0366; AVX-NEXT: vmovdqa %xmm0, (%rsp)367; AVX-NEXT: vmovaps (%rsp), %ymm0368; AVX-NEXT: movq %rbp, %rsp369; AVX-NEXT: popq %rbp370; AVX-NEXT: retq371 %1 = load <32 x i8>, ptr %src, align 16, !nontemporal !1372 ret <32 x i8> %1373}374 375; ZMM versions.376 377define <8 x double> @test_v8f64_align1(ptr %src) nounwind {378; SSE-LABEL: test_v8f64_align1:379; SSE: # %bb.0:380; SSE-NEXT: movups (%rdi), %xmm0381; SSE-NEXT: movups 16(%rdi), %xmm1382; SSE-NEXT: movups 32(%rdi), %xmm2383; SSE-NEXT: movups 48(%rdi), %xmm3384; SSE-NEXT: retq385;386; AVX1-LABEL: test_v8f64_align1:387; AVX1: # %bb.0:388; AVX1-NEXT: vmovups (%rdi), %ymm0389; AVX1-NEXT: vmovups 32(%rdi), %ymm1390; AVX1-NEXT: retq391;392; AVX2-LABEL: test_v8f64_align1:393; AVX2: # %bb.0:394; AVX2-NEXT: vmovups (%rdi), %ymm0395; AVX2-NEXT: vmovups 32(%rdi), %ymm1396; AVX2-NEXT: retq397;398; AVX512-LABEL: test_v8f64_align1:399; AVX512: # %bb.0:400; AVX512-NEXT: vmovups (%rdi), %zmm0401; AVX512-NEXT: retq402 %1 = load <8 x double>, ptr %src, align 1, !nontemporal !1403 ret <8 x double> %1404}405 406define <16 x float> @test_v16f32_align1(ptr %src) nounwind {407; SSE-LABEL: test_v16f32_align1:408; SSE: # %bb.0:409; SSE-NEXT: movups (%rdi), %xmm0410; SSE-NEXT: movups 16(%rdi), %xmm1411; SSE-NEXT: movups 32(%rdi), %xmm2412; SSE-NEXT: movups 48(%rdi), %xmm3413; SSE-NEXT: retq414;415; AVX1-LABEL: test_v16f32_align1:416; AVX1: # %bb.0:417; AVX1-NEXT: vmovups (%rdi), %ymm0418; AVX1-NEXT: vmovups 32(%rdi), %ymm1419; AVX1-NEXT: retq420;421; AVX2-LABEL: test_v16f32_align1:422; AVX2: # %bb.0:423; AVX2-NEXT: vmovups (%rdi), %ymm0424; AVX2-NEXT: vmovups 32(%rdi), %ymm1425; AVX2-NEXT: retq426;427; AVX512-LABEL: test_v16f32_align1:428; AVX512: # %bb.0:429; AVX512-NEXT: vmovups (%rdi), %zmm0430; AVX512-NEXT: retq431 %1 = load <16 x float>, ptr %src, align 1, !nontemporal !1432 ret <16 x float> %1433}434 435define <8 x i64> @test_v8i64_align1(ptr %src) nounwind {436; SSE-LABEL: test_v8i64_align1:437; SSE: # %bb.0:438; SSE-NEXT: movups (%rdi), %xmm0439; SSE-NEXT: movups 16(%rdi), %xmm1440; SSE-NEXT: movups 32(%rdi), %xmm2441; SSE-NEXT: movups 48(%rdi), %xmm3442; SSE-NEXT: retq443;444; AVX1-LABEL: test_v8i64_align1:445; AVX1: # %bb.0:446; AVX1-NEXT: vmovups (%rdi), %ymm0447; AVX1-NEXT: vmovups 32(%rdi), %ymm1448; AVX1-NEXT: retq449;450; AVX2-LABEL: test_v8i64_align1:451; AVX2: # %bb.0:452; AVX2-NEXT: vmovups (%rdi), %ymm0453; AVX2-NEXT: vmovups 32(%rdi), %ymm1454; AVX2-NEXT: retq455;456; AVX512-LABEL: test_v8i64_align1:457; AVX512: # %bb.0:458; AVX512-NEXT: vmovups (%rdi), %zmm0459; AVX512-NEXT: retq460 %1 = load <8 x i64>, ptr %src, align 1, !nontemporal !1461 ret <8 x i64> %1462}463 464define <16 x i32> @test_v16i32_align1(ptr %src) nounwind {465; SSE-LABEL: test_v16i32_align1:466; SSE: # %bb.0:467; SSE-NEXT: movups (%rdi), %xmm0468; SSE-NEXT: movups 16(%rdi), %xmm1469; SSE-NEXT: movups 32(%rdi), %xmm2470; SSE-NEXT: movups 48(%rdi), %xmm3471; SSE-NEXT: retq472;473; AVX1-LABEL: test_v16i32_align1:474; AVX1: # %bb.0:475; AVX1-NEXT: vmovups (%rdi), %ymm0476; AVX1-NEXT: vmovups 32(%rdi), %ymm1477; AVX1-NEXT: retq478;479; AVX2-LABEL: test_v16i32_align1:480; AVX2: # %bb.0:481; AVX2-NEXT: vmovups (%rdi), %ymm0482; AVX2-NEXT: vmovups 32(%rdi), %ymm1483; AVX2-NEXT: retq484;485; AVX512-LABEL: test_v16i32_align1:486; AVX512: # %bb.0:487; AVX512-NEXT: vmovups (%rdi), %zmm0488; AVX512-NEXT: retq489 %1 = load <16 x i32>, ptr %src, align 1, !nontemporal !1490 ret <16 x i32> %1491}492 493define <32 x i16> @test_v32i16_align1(ptr %src) nounwind {494; SSE-LABEL: test_v32i16_align1:495; SSE: # %bb.0:496; SSE-NEXT: movups (%rdi), %xmm0497; SSE-NEXT: movups 16(%rdi), %xmm1498; SSE-NEXT: movups 32(%rdi), %xmm2499; SSE-NEXT: movups 48(%rdi), %xmm3500; SSE-NEXT: retq501;502; AVX1-LABEL: test_v32i16_align1:503; AVX1: # %bb.0:504; AVX1-NEXT: vmovups (%rdi), %ymm0505; AVX1-NEXT: vmovups 32(%rdi), %ymm1506; AVX1-NEXT: retq507;508; AVX2-LABEL: test_v32i16_align1:509; AVX2: # %bb.0:510; AVX2-NEXT: vmovups (%rdi), %ymm0511; AVX2-NEXT: vmovups 32(%rdi), %ymm1512; AVX2-NEXT: retq513;514; AVX512-LABEL: test_v32i16_align1:515; AVX512: # %bb.0:516; AVX512-NEXT: vmovups (%rdi), %zmm0517; AVX512-NEXT: retq518 %1 = load <32 x i16>, ptr %src, align 1, !nontemporal !1519 ret <32 x i16> %1520}521 522define <64 x i8> @test_v64i8_align1(ptr %src) nounwind {523; SSE-LABEL: test_v64i8_align1:524; SSE: # %bb.0:525; SSE-NEXT: movups (%rdi), %xmm0526; SSE-NEXT: movups 16(%rdi), %xmm1527; SSE-NEXT: movups 32(%rdi), %xmm2528; SSE-NEXT: movups 48(%rdi), %xmm3529; SSE-NEXT: retq530;531; AVX1-LABEL: test_v64i8_align1:532; AVX1: # %bb.0:533; AVX1-NEXT: vmovups (%rdi), %ymm0534; AVX1-NEXT: vmovups 32(%rdi), %ymm1535; AVX1-NEXT: retq536;537; AVX2-LABEL: test_v64i8_align1:538; AVX2: # %bb.0:539; AVX2-NEXT: vmovups (%rdi), %ymm0540; AVX2-NEXT: vmovups 32(%rdi), %ymm1541; AVX2-NEXT: retq542;543; AVX512-LABEL: test_v64i8_align1:544; AVX512: # %bb.0:545; AVX512-NEXT: vmovups (%rdi), %zmm0546; AVX512-NEXT: retq547 %1 = load <64 x i8>, ptr %src, align 1, !nontemporal !1548 ret <64 x i8> %1549}550 551define <8 x double> @test_v8f64_align16(ptr %src) nounwind {552; SSE2-LABEL: test_v8f64_align16:553; SSE2: # %bb.0:554; SSE2-NEXT: movaps (%rdi), %xmm0555; SSE2-NEXT: movaps 16(%rdi), %xmm1556; SSE2-NEXT: movaps 32(%rdi), %xmm2557; SSE2-NEXT: movaps 48(%rdi), %xmm3558; SSE2-NEXT: retq559;560; SSE41-LABEL: test_v8f64_align16:561; SSE41: # %bb.0:562; SSE41-NEXT: movntdqa (%rdi), %xmm0563; SSE41-NEXT: movntdqa 16(%rdi), %xmm1564; SSE41-NEXT: movntdqa 32(%rdi), %xmm2565; SSE41-NEXT: movntdqa 48(%rdi), %xmm3566; SSE41-NEXT: retq567;568; AVX1-LABEL: test_v8f64_align16:569; AVX1: # %bb.0:570; AVX1-NEXT: pushq %rbp571; AVX1-NEXT: movq %rsp, %rbp572; AVX1-NEXT: andq $-32, %rsp573; AVX1-NEXT: subq $96, %rsp574; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0575; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)576; AVX1-NEXT: vmovntdqa (%rdi), %xmm0577; AVX1-NEXT: vmovdqa %xmm0, (%rsp)578; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0579; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)580; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0581; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)582; AVX1-NEXT: vmovaps (%rsp), %ymm0583; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1584; AVX1-NEXT: movq %rbp, %rsp585; AVX1-NEXT: popq %rbp586; AVX1-NEXT: retq587;588; AVX2-LABEL: test_v8f64_align16:589; AVX2: # %bb.0:590; AVX2-NEXT: pushq %rbp591; AVX2-NEXT: movq %rsp, %rbp592; AVX2-NEXT: andq $-32, %rsp593; AVX2-NEXT: subq $96, %rsp594; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0595; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)596; AVX2-NEXT: vmovntdqa (%rdi), %xmm0597; AVX2-NEXT: vmovdqa %xmm0, (%rsp)598; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0599; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)600; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0601; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)602; AVX2-NEXT: vmovaps (%rsp), %ymm0603; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1604; AVX2-NEXT: movq %rbp, %rsp605; AVX2-NEXT: popq %rbp606; AVX2-NEXT: retq607;608; AVX512-LABEL: test_v8f64_align16:609; AVX512: # %bb.0:610; AVX512-NEXT: pushq %rbp611; AVX512-NEXT: movq %rsp, %rbp612; AVX512-NEXT: andq $-64, %rsp613; AVX512-NEXT: subq $128, %rsp614; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm0615; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)616; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm0617; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)618; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm0619; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)620; AVX512-NEXT: vmovntdqa (%rdi), %xmm0621; AVX512-NEXT: vmovdqa %xmm0, (%rsp)622; AVX512-NEXT: vmovaps (%rsp), %zmm0623; AVX512-NEXT: movq %rbp, %rsp624; AVX512-NEXT: popq %rbp625; AVX512-NEXT: retq626 %1 = load <8 x double>, ptr %src, align 16, !nontemporal !1627 ret <8 x double> %1628}629 630define <16 x float> @test_v16f32_align16(ptr %src) nounwind {631; SSE2-LABEL: test_v16f32_align16:632; SSE2: # %bb.0:633; SSE2-NEXT: movaps (%rdi), %xmm0634; SSE2-NEXT: movaps 16(%rdi), %xmm1635; SSE2-NEXT: movaps 32(%rdi), %xmm2636; SSE2-NEXT: movaps 48(%rdi), %xmm3637; SSE2-NEXT: retq638;639; SSE41-LABEL: test_v16f32_align16:640; SSE41: # %bb.0:641; SSE41-NEXT: movntdqa (%rdi), %xmm0642; SSE41-NEXT: movntdqa 16(%rdi), %xmm1643; SSE41-NEXT: movntdqa 32(%rdi), %xmm2644; SSE41-NEXT: movntdqa 48(%rdi), %xmm3645; SSE41-NEXT: retq646;647; AVX1-LABEL: test_v16f32_align16:648; AVX1: # %bb.0:649; AVX1-NEXT: pushq %rbp650; AVX1-NEXT: movq %rsp, %rbp651; AVX1-NEXT: andq $-32, %rsp652; AVX1-NEXT: subq $96, %rsp653; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0654; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)655; AVX1-NEXT: vmovntdqa (%rdi), %xmm0656; AVX1-NEXT: vmovdqa %xmm0, (%rsp)657; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0658; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)659; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0660; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)661; AVX1-NEXT: vmovaps (%rsp), %ymm0662; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1663; AVX1-NEXT: movq %rbp, %rsp664; AVX1-NEXT: popq %rbp665; AVX1-NEXT: retq666;667; AVX2-LABEL: test_v16f32_align16:668; AVX2: # %bb.0:669; AVX2-NEXT: pushq %rbp670; AVX2-NEXT: movq %rsp, %rbp671; AVX2-NEXT: andq $-32, %rsp672; AVX2-NEXT: subq $96, %rsp673; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0674; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)675; AVX2-NEXT: vmovntdqa (%rdi), %xmm0676; AVX2-NEXT: vmovdqa %xmm0, (%rsp)677; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0678; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)679; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0680; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)681; AVX2-NEXT: vmovaps (%rsp), %ymm0682; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1683; AVX2-NEXT: movq %rbp, %rsp684; AVX2-NEXT: popq %rbp685; AVX2-NEXT: retq686;687; AVX512-LABEL: test_v16f32_align16:688; AVX512: # %bb.0:689; AVX512-NEXT: pushq %rbp690; AVX512-NEXT: movq %rsp, %rbp691; AVX512-NEXT: andq $-64, %rsp692; AVX512-NEXT: subq $128, %rsp693; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm0694; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)695; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm0696; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)697; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm0698; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)699; AVX512-NEXT: vmovntdqa (%rdi), %xmm0700; AVX512-NEXT: vmovdqa %xmm0, (%rsp)701; AVX512-NEXT: vmovaps (%rsp), %zmm0702; AVX512-NEXT: movq %rbp, %rsp703; AVX512-NEXT: popq %rbp704; AVX512-NEXT: retq705 %1 = load <16 x float>, ptr %src, align 16, !nontemporal !1706 ret <16 x float> %1707}708 709define <8 x i64> @test_v8i64_align16(ptr %src) nounwind {710; SSE2-LABEL: test_v8i64_align16:711; SSE2: # %bb.0:712; SSE2-NEXT: movaps (%rdi), %xmm0713; SSE2-NEXT: movaps 16(%rdi), %xmm1714; SSE2-NEXT: movaps 32(%rdi), %xmm2715; SSE2-NEXT: movaps 48(%rdi), %xmm3716; SSE2-NEXT: retq717;718; SSE41-LABEL: test_v8i64_align16:719; SSE41: # %bb.0:720; SSE41-NEXT: movntdqa (%rdi), %xmm0721; SSE41-NEXT: movntdqa 16(%rdi), %xmm1722; SSE41-NEXT: movntdqa 32(%rdi), %xmm2723; SSE41-NEXT: movntdqa 48(%rdi), %xmm3724; SSE41-NEXT: retq725;726; AVX1-LABEL: test_v8i64_align16:727; AVX1: # %bb.0:728; AVX1-NEXT: pushq %rbp729; AVX1-NEXT: movq %rsp, %rbp730; AVX1-NEXT: andq $-32, %rsp731; AVX1-NEXT: subq $96, %rsp732; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0733; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)734; AVX1-NEXT: vmovntdqa (%rdi), %xmm0735; AVX1-NEXT: vmovdqa %xmm0, (%rsp)736; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0737; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)738; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0739; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)740; AVX1-NEXT: vmovaps (%rsp), %ymm0741; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1742; AVX1-NEXT: movq %rbp, %rsp743; AVX1-NEXT: popq %rbp744; AVX1-NEXT: retq745;746; AVX2-LABEL: test_v8i64_align16:747; AVX2: # %bb.0:748; AVX2-NEXT: pushq %rbp749; AVX2-NEXT: movq %rsp, %rbp750; AVX2-NEXT: andq $-32, %rsp751; AVX2-NEXT: subq $96, %rsp752; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0753; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)754; AVX2-NEXT: vmovntdqa (%rdi), %xmm0755; AVX2-NEXT: vmovdqa %xmm0, (%rsp)756; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0757; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)758; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0759; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)760; AVX2-NEXT: vmovaps (%rsp), %ymm0761; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1762; AVX2-NEXT: movq %rbp, %rsp763; AVX2-NEXT: popq %rbp764; AVX2-NEXT: retq765;766; AVX512-LABEL: test_v8i64_align16:767; AVX512: # %bb.0:768; AVX512-NEXT: pushq %rbp769; AVX512-NEXT: movq %rsp, %rbp770; AVX512-NEXT: andq $-64, %rsp771; AVX512-NEXT: subq $128, %rsp772; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm0773; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)774; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm0775; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)776; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm0777; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)778; AVX512-NEXT: vmovntdqa (%rdi), %xmm0779; AVX512-NEXT: vmovdqa %xmm0, (%rsp)780; AVX512-NEXT: vmovaps (%rsp), %zmm0781; AVX512-NEXT: movq %rbp, %rsp782; AVX512-NEXT: popq %rbp783; AVX512-NEXT: retq784 %1 = load <8 x i64>, ptr %src, align 16, !nontemporal !1785 ret <8 x i64> %1786}787 788define <16 x i32> @test_v16i32_align16(ptr %src) nounwind {789; SSE2-LABEL: test_v16i32_align16:790; SSE2: # %bb.0:791; SSE2-NEXT: movaps (%rdi), %xmm0792; SSE2-NEXT: movaps 16(%rdi), %xmm1793; SSE2-NEXT: movaps 32(%rdi), %xmm2794; SSE2-NEXT: movaps 48(%rdi), %xmm3795; SSE2-NEXT: retq796;797; SSE41-LABEL: test_v16i32_align16:798; SSE41: # %bb.0:799; SSE41-NEXT: movntdqa (%rdi), %xmm0800; SSE41-NEXT: movntdqa 16(%rdi), %xmm1801; SSE41-NEXT: movntdqa 32(%rdi), %xmm2802; SSE41-NEXT: movntdqa 48(%rdi), %xmm3803; SSE41-NEXT: retq804;805; AVX1-LABEL: test_v16i32_align16:806; AVX1: # %bb.0:807; AVX1-NEXT: pushq %rbp808; AVX1-NEXT: movq %rsp, %rbp809; AVX1-NEXT: andq $-32, %rsp810; AVX1-NEXT: subq $96, %rsp811; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0812; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)813; AVX1-NEXT: vmovntdqa (%rdi), %xmm0814; AVX1-NEXT: vmovdqa %xmm0, (%rsp)815; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0816; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)817; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0818; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)819; AVX1-NEXT: vmovaps (%rsp), %ymm0820; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1821; AVX1-NEXT: movq %rbp, %rsp822; AVX1-NEXT: popq %rbp823; AVX1-NEXT: retq824;825; AVX2-LABEL: test_v16i32_align16:826; AVX2: # %bb.0:827; AVX2-NEXT: pushq %rbp828; AVX2-NEXT: movq %rsp, %rbp829; AVX2-NEXT: andq $-32, %rsp830; AVX2-NEXT: subq $96, %rsp831; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0832; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)833; AVX2-NEXT: vmovntdqa (%rdi), %xmm0834; AVX2-NEXT: vmovdqa %xmm0, (%rsp)835; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0836; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)837; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0838; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)839; AVX2-NEXT: vmovaps (%rsp), %ymm0840; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1841; AVX2-NEXT: movq %rbp, %rsp842; AVX2-NEXT: popq %rbp843; AVX2-NEXT: retq844;845; AVX512-LABEL: test_v16i32_align16:846; AVX512: # %bb.0:847; AVX512-NEXT: pushq %rbp848; AVX512-NEXT: movq %rsp, %rbp849; AVX512-NEXT: andq $-64, %rsp850; AVX512-NEXT: subq $128, %rsp851; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm0852; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)853; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm0854; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)855; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm0856; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)857; AVX512-NEXT: vmovntdqa (%rdi), %xmm0858; AVX512-NEXT: vmovdqa %xmm0, (%rsp)859; AVX512-NEXT: vmovaps (%rsp), %zmm0860; AVX512-NEXT: movq %rbp, %rsp861; AVX512-NEXT: popq %rbp862; AVX512-NEXT: retq863 %1 = load <16 x i32>, ptr %src, align 16, !nontemporal !1864 ret <16 x i32> %1865}866 867define <32 x i16> @test_v32i16_align16(ptr %src) nounwind {868; SSE2-LABEL: test_v32i16_align16:869; SSE2: # %bb.0:870; SSE2-NEXT: movaps (%rdi), %xmm0871; SSE2-NEXT: movaps 16(%rdi), %xmm1872; SSE2-NEXT: movaps 32(%rdi), %xmm2873; SSE2-NEXT: movaps 48(%rdi), %xmm3874; SSE2-NEXT: retq875;876; SSE41-LABEL: test_v32i16_align16:877; SSE41: # %bb.0:878; SSE41-NEXT: movntdqa (%rdi), %xmm0879; SSE41-NEXT: movntdqa 16(%rdi), %xmm1880; SSE41-NEXT: movntdqa 32(%rdi), %xmm2881; SSE41-NEXT: movntdqa 48(%rdi), %xmm3882; SSE41-NEXT: retq883;884; AVX1-LABEL: test_v32i16_align16:885; AVX1: # %bb.0:886; AVX1-NEXT: pushq %rbp887; AVX1-NEXT: movq %rsp, %rbp888; AVX1-NEXT: andq $-32, %rsp889; AVX1-NEXT: subq $96, %rsp890; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0891; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)892; AVX1-NEXT: vmovntdqa (%rdi), %xmm0893; AVX1-NEXT: vmovdqa %xmm0, (%rsp)894; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0895; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)896; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0897; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)898; AVX1-NEXT: vmovaps (%rsp), %ymm0899; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1900; AVX1-NEXT: movq %rbp, %rsp901; AVX1-NEXT: popq %rbp902; AVX1-NEXT: retq903;904; AVX2-LABEL: test_v32i16_align16:905; AVX2: # %bb.0:906; AVX2-NEXT: pushq %rbp907; AVX2-NEXT: movq %rsp, %rbp908; AVX2-NEXT: andq $-32, %rsp909; AVX2-NEXT: subq $96, %rsp910; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0911; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)912; AVX2-NEXT: vmovntdqa (%rdi), %xmm0913; AVX2-NEXT: vmovdqa %xmm0, (%rsp)914; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0915; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)916; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0917; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)918; AVX2-NEXT: vmovaps (%rsp), %ymm0919; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1920; AVX2-NEXT: movq %rbp, %rsp921; AVX2-NEXT: popq %rbp922; AVX2-NEXT: retq923;924; AVX512-LABEL: test_v32i16_align16:925; AVX512: # %bb.0:926; AVX512-NEXT: pushq %rbp927; AVX512-NEXT: movq %rsp, %rbp928; AVX512-NEXT: andq $-64, %rsp929; AVX512-NEXT: subq $128, %rsp930; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm0931; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)932; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm0933; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)934; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm0935; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)936; AVX512-NEXT: vmovntdqa (%rdi), %xmm0937; AVX512-NEXT: vmovdqa %xmm0, (%rsp)938; AVX512-NEXT: vmovaps (%rsp), %zmm0939; AVX512-NEXT: movq %rbp, %rsp940; AVX512-NEXT: popq %rbp941; AVX512-NEXT: retq942 %1 = load <32 x i16>, ptr %src, align 16, !nontemporal !1943 ret <32 x i16> %1944}945 946define <64 x i8> @test_v64i8_align16(ptr %src) nounwind {947; SSE2-LABEL: test_v64i8_align16:948; SSE2: # %bb.0:949; SSE2-NEXT: movaps (%rdi), %xmm0950; SSE2-NEXT: movaps 16(%rdi), %xmm1951; SSE2-NEXT: movaps 32(%rdi), %xmm2952; SSE2-NEXT: movaps 48(%rdi), %xmm3953; SSE2-NEXT: retq954;955; SSE41-LABEL: test_v64i8_align16:956; SSE41: # %bb.0:957; SSE41-NEXT: movntdqa (%rdi), %xmm0958; SSE41-NEXT: movntdqa 16(%rdi), %xmm1959; SSE41-NEXT: movntdqa 32(%rdi), %xmm2960; SSE41-NEXT: movntdqa 48(%rdi), %xmm3961; SSE41-NEXT: retq962;963; AVX1-LABEL: test_v64i8_align16:964; AVX1: # %bb.0:965; AVX1-NEXT: pushq %rbp966; AVX1-NEXT: movq %rsp, %rbp967; AVX1-NEXT: andq $-32, %rsp968; AVX1-NEXT: subq $96, %rsp969; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0970; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)971; AVX1-NEXT: vmovntdqa (%rdi), %xmm0972; AVX1-NEXT: vmovdqa %xmm0, (%rsp)973; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm0974; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)975; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm0976; AVX1-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)977; AVX1-NEXT: vmovaps (%rsp), %ymm0978; AVX1-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1979; AVX1-NEXT: movq %rbp, %rsp980; AVX1-NEXT: popq %rbp981; AVX1-NEXT: retq982;983; AVX2-LABEL: test_v64i8_align16:984; AVX2: # %bb.0:985; AVX2-NEXT: pushq %rbp986; AVX2-NEXT: movq %rsp, %rbp987; AVX2-NEXT: andq $-32, %rsp988; AVX2-NEXT: subq $96, %rsp989; AVX2-NEXT: vmovntdqa 16(%rdi), %xmm0990; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)991; AVX2-NEXT: vmovntdqa (%rdi), %xmm0992; AVX2-NEXT: vmovdqa %xmm0, (%rsp)993; AVX2-NEXT: vmovntdqa 48(%rdi), %xmm0994; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)995; AVX2-NEXT: vmovntdqa 32(%rdi), %xmm0996; AVX2-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)997; AVX2-NEXT: vmovaps (%rsp), %ymm0998; AVX2-NEXT: vmovaps {{[0-9]+}}(%rsp), %ymm1999; AVX2-NEXT: movq %rbp, %rsp1000; AVX2-NEXT: popq %rbp1001; AVX2-NEXT: retq1002;1003; AVX512-LABEL: test_v64i8_align16:1004; AVX512: # %bb.0:1005; AVX512-NEXT: pushq %rbp1006; AVX512-NEXT: movq %rsp, %rbp1007; AVX512-NEXT: andq $-64, %rsp1008; AVX512-NEXT: subq $128, %rsp1009; AVX512-NEXT: vmovntdqa 48(%rdi), %xmm01010; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)1011; AVX512-NEXT: vmovntdqa 32(%rdi), %xmm01012; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)1013; AVX512-NEXT: vmovntdqa 16(%rdi), %xmm01014; AVX512-NEXT: vmovdqa %xmm0, {{[0-9]+}}(%rsp)1015; AVX512-NEXT: vmovntdqa (%rdi), %xmm01016; AVX512-NEXT: vmovdqa %xmm0, (%rsp)1017; AVX512-NEXT: vmovaps (%rsp), %zmm01018; AVX512-NEXT: movq %rbp, %rsp1019; AVX512-NEXT: popq %rbp1020; AVX512-NEXT: retq1021 %1 = load <64 x i8>, ptr %src, align 16, !nontemporal !11022 ret <64 x i8> %11023}1024 1025define <8 x double> @test_v8f64_align32(ptr %src) nounwind {1026; SSE2-LABEL: test_v8f64_align32:1027; SSE2: # %bb.0:1028; SSE2-NEXT: movaps (%rdi), %xmm01029; SSE2-NEXT: movaps 16(%rdi), %xmm11030; SSE2-NEXT: movaps 32(%rdi), %xmm21031; SSE2-NEXT: movaps 48(%rdi), %xmm31032; SSE2-NEXT: retq1033;1034; SSE41-LABEL: test_v8f64_align32:1035; SSE41: # %bb.0:1036; SSE41-NEXT: movntdqa (%rdi), %xmm01037; SSE41-NEXT: movntdqa 16(%rdi), %xmm11038; SSE41-NEXT: movntdqa 32(%rdi), %xmm21039; SSE41-NEXT: movntdqa 48(%rdi), %xmm31040; SSE41-NEXT: retq1041;1042; AVX1-LABEL: test_v8f64_align32:1043; AVX1: # %bb.0:1044; AVX1-NEXT: vmovntdqa (%rdi), %xmm01045; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11046; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01047; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11048; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21049; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11050; AVX1-NEXT: retq1051;1052; AVX2-LABEL: test_v8f64_align32:1053; AVX2: # %bb.0:1054; AVX2-NEXT: vmovntdqa (%rdi), %ymm01055; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11056; AVX2-NEXT: retq1057;1058; AVX512-LABEL: test_v8f64_align32:1059; AVX512: # %bb.0:1060; AVX512-NEXT: pushq %rbp1061; AVX512-NEXT: movq %rsp, %rbp1062; AVX512-NEXT: andq $-64, %rsp1063; AVX512-NEXT: subq $128, %rsp1064; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01065; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1066; AVX512-NEXT: vmovntdqa (%rdi), %ymm01067; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1068; AVX512-NEXT: vmovaps (%rsp), %zmm01069; AVX512-NEXT: movq %rbp, %rsp1070; AVX512-NEXT: popq %rbp1071; AVX512-NEXT: retq1072 %1 = load <8 x double>, ptr %src, align 32, !nontemporal !11073 ret <8 x double> %11074}1075 1076define <16 x float> @test_v16f32_align32(ptr %src) nounwind {1077; SSE2-LABEL: test_v16f32_align32:1078; SSE2: # %bb.0:1079; SSE2-NEXT: movaps (%rdi), %xmm01080; SSE2-NEXT: movaps 16(%rdi), %xmm11081; SSE2-NEXT: movaps 32(%rdi), %xmm21082; SSE2-NEXT: movaps 48(%rdi), %xmm31083; SSE2-NEXT: retq1084;1085; SSE41-LABEL: test_v16f32_align32:1086; SSE41: # %bb.0:1087; SSE41-NEXT: movntdqa (%rdi), %xmm01088; SSE41-NEXT: movntdqa 16(%rdi), %xmm11089; SSE41-NEXT: movntdqa 32(%rdi), %xmm21090; SSE41-NEXT: movntdqa 48(%rdi), %xmm31091; SSE41-NEXT: retq1092;1093; AVX1-LABEL: test_v16f32_align32:1094; AVX1: # %bb.0:1095; AVX1-NEXT: vmovntdqa (%rdi), %xmm01096; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11097; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01098; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11099; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21100; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11101; AVX1-NEXT: retq1102;1103; AVX2-LABEL: test_v16f32_align32:1104; AVX2: # %bb.0:1105; AVX2-NEXT: vmovntdqa (%rdi), %ymm01106; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11107; AVX2-NEXT: retq1108;1109; AVX512-LABEL: test_v16f32_align32:1110; AVX512: # %bb.0:1111; AVX512-NEXT: pushq %rbp1112; AVX512-NEXT: movq %rsp, %rbp1113; AVX512-NEXT: andq $-64, %rsp1114; AVX512-NEXT: subq $128, %rsp1115; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01116; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1117; AVX512-NEXT: vmovntdqa (%rdi), %ymm01118; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1119; AVX512-NEXT: vmovaps (%rsp), %zmm01120; AVX512-NEXT: movq %rbp, %rsp1121; AVX512-NEXT: popq %rbp1122; AVX512-NEXT: retq1123 %1 = load <16 x float>, ptr %src, align 32, !nontemporal !11124 ret <16 x float> %11125}1126 1127define <8 x i64> @test_v8i64_align32(ptr %src) nounwind {1128; SSE2-LABEL: test_v8i64_align32:1129; SSE2: # %bb.0:1130; SSE2-NEXT: movaps (%rdi), %xmm01131; SSE2-NEXT: movaps 16(%rdi), %xmm11132; SSE2-NEXT: movaps 32(%rdi), %xmm21133; SSE2-NEXT: movaps 48(%rdi), %xmm31134; SSE2-NEXT: retq1135;1136; SSE41-LABEL: test_v8i64_align32:1137; SSE41: # %bb.0:1138; SSE41-NEXT: movntdqa (%rdi), %xmm01139; SSE41-NEXT: movntdqa 16(%rdi), %xmm11140; SSE41-NEXT: movntdqa 32(%rdi), %xmm21141; SSE41-NEXT: movntdqa 48(%rdi), %xmm31142; SSE41-NEXT: retq1143;1144; AVX1-LABEL: test_v8i64_align32:1145; AVX1: # %bb.0:1146; AVX1-NEXT: vmovntdqa (%rdi), %xmm01147; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11148; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01149; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11150; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21151; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11152; AVX1-NEXT: retq1153;1154; AVX2-LABEL: test_v8i64_align32:1155; AVX2: # %bb.0:1156; AVX2-NEXT: vmovntdqa (%rdi), %ymm01157; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11158; AVX2-NEXT: retq1159;1160; AVX512-LABEL: test_v8i64_align32:1161; AVX512: # %bb.0:1162; AVX512-NEXT: pushq %rbp1163; AVX512-NEXT: movq %rsp, %rbp1164; AVX512-NEXT: andq $-64, %rsp1165; AVX512-NEXT: subq $128, %rsp1166; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01167; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1168; AVX512-NEXT: vmovntdqa (%rdi), %ymm01169; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1170; AVX512-NEXT: vmovaps (%rsp), %zmm01171; AVX512-NEXT: movq %rbp, %rsp1172; AVX512-NEXT: popq %rbp1173; AVX512-NEXT: retq1174 %1 = load <8 x i64>, ptr %src, align 32, !nontemporal !11175 ret <8 x i64> %11176}1177 1178define <16 x i32> @test_v16i32_align32(ptr %src) nounwind {1179; SSE2-LABEL: test_v16i32_align32:1180; SSE2: # %bb.0:1181; SSE2-NEXT: movaps (%rdi), %xmm01182; SSE2-NEXT: movaps 16(%rdi), %xmm11183; SSE2-NEXT: movaps 32(%rdi), %xmm21184; SSE2-NEXT: movaps 48(%rdi), %xmm31185; SSE2-NEXT: retq1186;1187; SSE41-LABEL: test_v16i32_align32:1188; SSE41: # %bb.0:1189; SSE41-NEXT: movntdqa (%rdi), %xmm01190; SSE41-NEXT: movntdqa 16(%rdi), %xmm11191; SSE41-NEXT: movntdqa 32(%rdi), %xmm21192; SSE41-NEXT: movntdqa 48(%rdi), %xmm31193; SSE41-NEXT: retq1194;1195; AVX1-LABEL: test_v16i32_align32:1196; AVX1: # %bb.0:1197; AVX1-NEXT: vmovntdqa (%rdi), %xmm01198; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11199; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01200; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11201; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21202; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11203; AVX1-NEXT: retq1204;1205; AVX2-LABEL: test_v16i32_align32:1206; AVX2: # %bb.0:1207; AVX2-NEXT: vmovntdqa (%rdi), %ymm01208; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11209; AVX2-NEXT: retq1210;1211; AVX512-LABEL: test_v16i32_align32:1212; AVX512: # %bb.0:1213; AVX512-NEXT: pushq %rbp1214; AVX512-NEXT: movq %rsp, %rbp1215; AVX512-NEXT: andq $-64, %rsp1216; AVX512-NEXT: subq $128, %rsp1217; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01218; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1219; AVX512-NEXT: vmovntdqa (%rdi), %ymm01220; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1221; AVX512-NEXT: vmovaps (%rsp), %zmm01222; AVX512-NEXT: movq %rbp, %rsp1223; AVX512-NEXT: popq %rbp1224; AVX512-NEXT: retq1225 %1 = load <16 x i32>, ptr %src, align 32, !nontemporal !11226 ret <16 x i32> %11227}1228 1229define <32 x i16> @test_v32i16_align32(ptr %src) nounwind {1230; SSE2-LABEL: test_v32i16_align32:1231; SSE2: # %bb.0:1232; SSE2-NEXT: movaps (%rdi), %xmm01233; SSE2-NEXT: movaps 16(%rdi), %xmm11234; SSE2-NEXT: movaps 32(%rdi), %xmm21235; SSE2-NEXT: movaps 48(%rdi), %xmm31236; SSE2-NEXT: retq1237;1238; SSE41-LABEL: test_v32i16_align32:1239; SSE41: # %bb.0:1240; SSE41-NEXT: movntdqa (%rdi), %xmm01241; SSE41-NEXT: movntdqa 16(%rdi), %xmm11242; SSE41-NEXT: movntdqa 32(%rdi), %xmm21243; SSE41-NEXT: movntdqa 48(%rdi), %xmm31244; SSE41-NEXT: retq1245;1246; AVX1-LABEL: test_v32i16_align32:1247; AVX1: # %bb.0:1248; AVX1-NEXT: vmovntdqa (%rdi), %xmm01249; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11250; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01251; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11252; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21253; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11254; AVX1-NEXT: retq1255;1256; AVX2-LABEL: test_v32i16_align32:1257; AVX2: # %bb.0:1258; AVX2-NEXT: vmovntdqa (%rdi), %ymm01259; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11260; AVX2-NEXT: retq1261;1262; AVX512-LABEL: test_v32i16_align32:1263; AVX512: # %bb.0:1264; AVX512-NEXT: pushq %rbp1265; AVX512-NEXT: movq %rsp, %rbp1266; AVX512-NEXT: andq $-64, %rsp1267; AVX512-NEXT: subq $128, %rsp1268; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01269; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1270; AVX512-NEXT: vmovntdqa (%rdi), %ymm01271; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1272; AVX512-NEXT: vmovaps (%rsp), %zmm01273; AVX512-NEXT: movq %rbp, %rsp1274; AVX512-NEXT: popq %rbp1275; AVX512-NEXT: retq1276 %1 = load <32 x i16>, ptr %src, align 32, !nontemporal !11277 ret <32 x i16> %11278}1279 1280define <64 x i8> @test_v64i8_align32(ptr %src) nounwind {1281; SSE2-LABEL: test_v64i8_align32:1282; SSE2: # %bb.0:1283; SSE2-NEXT: movaps (%rdi), %xmm01284; SSE2-NEXT: movaps 16(%rdi), %xmm11285; SSE2-NEXT: movaps 32(%rdi), %xmm21286; SSE2-NEXT: movaps 48(%rdi), %xmm31287; SSE2-NEXT: retq1288;1289; SSE41-LABEL: test_v64i8_align32:1290; SSE41: # %bb.0:1291; SSE41-NEXT: movntdqa (%rdi), %xmm01292; SSE41-NEXT: movntdqa 16(%rdi), %xmm11293; SSE41-NEXT: movntdqa 32(%rdi), %xmm21294; SSE41-NEXT: movntdqa 48(%rdi), %xmm31295; SSE41-NEXT: retq1296;1297; AVX1-LABEL: test_v64i8_align32:1298; AVX1: # %bb.0:1299; AVX1-NEXT: vmovntdqa (%rdi), %xmm01300; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm11301; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm01302; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm11303; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm21304; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm11305; AVX1-NEXT: retq1306;1307; AVX2-LABEL: test_v64i8_align32:1308; AVX2: # %bb.0:1309; AVX2-NEXT: vmovntdqa (%rdi), %ymm01310; AVX2-NEXT: vmovntdqa 32(%rdi), %ymm11311; AVX2-NEXT: retq1312;1313; AVX512-LABEL: test_v64i8_align32:1314; AVX512: # %bb.0:1315; AVX512-NEXT: pushq %rbp1316; AVX512-NEXT: movq %rsp, %rbp1317; AVX512-NEXT: andq $-64, %rsp1318; AVX512-NEXT: subq $128, %rsp1319; AVX512-NEXT: vmovntdqa 32(%rdi), %ymm01320; AVX512-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)1321; AVX512-NEXT: vmovntdqa (%rdi), %ymm01322; AVX512-NEXT: vmovdqa %ymm0, (%rsp)1323; AVX512-NEXT: vmovaps (%rsp), %zmm01324; AVX512-NEXT: movq %rbp, %rsp1325; AVX512-NEXT: popq %rbp1326; AVX512-NEXT: retq1327 %1 = load <64 x i8>, ptr %src, align 32, !nontemporal !11328 ret <64 x i8> %11329}1330 1331!1 = !{i32 1}1332