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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X644 5define i128 @mulhioverflow(i64 %a, i64 %b, i64 %c) nounwind {6; X32-LABEL: mulhioverflow:7; X32: # %bb.0:8; X32-NEXT: pushl %ebp9; X32-NEXT: pushl %ebx10; X32-NEXT: pushl %edi11; X32-NEXT: pushl %esi12; X32-NEXT: movl {{[0-9]+}}(%esp), %esi13; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx14; X32-NEXT: movl {{[0-9]+}}(%esp), %edi15; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx16; X32-NEXT: movl %esi, %eax17; X32-NEXT: mull %edi18; X32-NEXT: movl %edx, %ebp19; X32-NEXT: movl %ebx, %eax20; X32-NEXT: mull %edi21; X32-NEXT: movl %edx, %edi22; X32-NEXT: movl %eax, %ebx23; X32-NEXT: addl %ebp, %ebx24; X32-NEXT: adcl $0, %edi25; X32-NEXT: movl %esi, %eax26; X32-NEXT: mull %ecx27; X32-NEXT: movl %edx, %esi28; X32-NEXT: addl %ebx, %eax29; X32-NEXT: adcl %edi, %esi30; X32-NEXT: setb %bl31; X32-NEXT: movl {{[0-9]+}}(%esp), %eax32; X32-NEXT: mull %ecx33; X32-NEXT: addl %esi, %eax34; X32-NEXT: movzbl %bl, %ecx35; X32-NEXT: adcl %ecx, %edx36; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx37; X32-NEXT: andl $1, %ecx38; X32-NEXT: addl %eax, %ecx39; X32-NEXT: movl {{[0-9]+}}(%esp), %eax40; X32-NEXT: movl %ecx, (%eax)41; X32-NEXT: adcl $0, %edx42; X32-NEXT: movl %edx, 4(%eax)43; X32-NEXT: setb %cl44; X32-NEXT: movzbl %cl, %ecx45; X32-NEXT: movl %ecx, 8(%eax)46; X32-NEXT: movl $0, 12(%eax)47; X32-NEXT: popl %esi48; X32-NEXT: popl %edi49; X32-NEXT: popl %ebx50; X32-NEXT: popl %ebp51; X32-NEXT: retl $452;53; X64-LABEL: mulhioverflow:54; X64: # %bb.0:55; X64-NEXT: movq %rdx, %rcx56; X64-NEXT: movq %rdi, %rax57; X64-NEXT: mulq %rsi58; X64-NEXT: andl $1, %ecx59; X64-NEXT: addq %rdx, %rcx60; X64-NEXT: movq %rcx, %rax61; X64-NEXT: xorl %edx, %edx62; X64-NEXT: retq63 %1 = zext i64 %a to i12864 %2 = zext i64 %b to i12865 %3 = mul i128 %1, %266 %4 = lshr i128 %3, 6467 %5 = and i64 %c, 168 %6 = zext i64 %5 to i12869 %7 = add i128 %4, %670 ret i128 %771}72