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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s3 4; These tests use cmp+adc/sbb in place of test+set+add/sub. Should this transform5; be enabled by micro-architecture rather than as part of generic lowering/isel?6 7define i8 @test1(i8 %a, i8 %b) nounwind {8; CHECK-LABEL: test1:9; CHECK: # %bb.0:10; CHECK-NEXT: movl %esi, %eax11; CHECK-NEXT: cmpb %al, %dil12; CHECK-NEXT: adcb $0, %al13; CHECK-NEXT: # kill: def $al killed $al killed $eax14; CHECK-NEXT: retq15 %cmp = icmp ult i8 %a, %b16 %cond = zext i1 %cmp to i817 %add = add i8 %cond, %b18 ret i8 %add19}20 21define i32 @test2(i32 %a, i32 %b) nounwind {22; CHECK-LABEL: test2:23; CHECK: # %bb.0:24; CHECK-NEXT: movl %esi, %eax25; CHECK-NEXT: cmpl %esi, %edi26; CHECK-NEXT: adcl $0, %eax27; CHECK-NEXT: retq28 %cmp = icmp ult i32 %a, %b29 %cond = zext i1 %cmp to i3230 %add = add i32 %cond, %b31 ret i32 %add32}33 34define i64 @test3(i64 %a, i64 %b) nounwind {35; CHECK-LABEL: test3:36; CHECK: # %bb.0:37; CHECK-NEXT: movq %rsi, %rax38; CHECK-NEXT: cmpq %rsi, %rdi39; CHECK-NEXT: adcq $0, %rax40; CHECK-NEXT: retq41 %cmp = icmp ult i64 %a, %b42 %conv = zext i1 %cmp to i6443 %add = add i64 %conv, %b44 ret i64 %add45}46 47define i8 @test4(i8 %a, i8 %b) nounwind {48; CHECK-LABEL: test4:49; CHECK: # %bb.0:50; CHECK-NEXT: movl %esi, %eax51; CHECK-NEXT: cmpb %al, %dil52; CHECK-NEXT: sbbb $0, %al53; CHECK-NEXT: # kill: def $al killed $al killed $eax54; CHECK-NEXT: retq55 %cmp = icmp ult i8 %a, %b56 %cond = zext i1 %cmp to i857 %sub = sub i8 %b, %cond58 ret i8 %sub59}60 61define i32 @test5(i32 %a, i32 %b) nounwind {62; CHECK-LABEL: test5:63; CHECK: # %bb.0:64; CHECK-NEXT: movl %esi, %eax65; CHECK-NEXT: cmpl %esi, %edi66; CHECK-NEXT: sbbl $0, %eax67; CHECK-NEXT: retq68 %cmp = icmp ult i32 %a, %b69 %cond = zext i1 %cmp to i3270 %sub = sub i32 %b, %cond71 ret i32 %sub72}73 74define i64 @test6(i64 %a, i64 %b) nounwind {75; CHECK-LABEL: test6:76; CHECK: # %bb.0:77; CHECK-NEXT: movq %rsi, %rax78; CHECK-NEXT: cmpq %rsi, %rdi79; CHECK-NEXT: sbbq $0, %rax80; CHECK-NEXT: retq81 %cmp = icmp ult i64 %a, %b82 %conv = zext i1 %cmp to i6483 %sub = sub i64 %b, %conv84 ret i64 %sub85}86 87define i8 @test7(i8 %a, i8 %b) nounwind {88; CHECK-LABEL: test7:89; CHECK: # %bb.0:90; CHECK-NEXT: movl %esi, %eax91; CHECK-NEXT: cmpb %al, %dil92; CHECK-NEXT: adcb $0, %al93; CHECK-NEXT: # kill: def $al killed $al killed $eax94; CHECK-NEXT: retq95 %cmp = icmp ult i8 %a, %b96 %cond = sext i1 %cmp to i897 %sub = sub i8 %b, %cond98 ret i8 %sub99}100 101define i32 @test8(i32 %a, i32 %b) nounwind {102; CHECK-LABEL: test8:103; CHECK: # %bb.0:104; CHECK-NEXT: movl %esi, %eax105; CHECK-NEXT: cmpl %esi, %edi106; CHECK-NEXT: adcl $0, %eax107; CHECK-NEXT: retq108 %cmp = icmp ult i32 %a, %b109 %cond = sext i1 %cmp to i32110 %sub = sub i32 %b, %cond111 ret i32 %sub112}113 114define i64 @test9(i64 %a, i64 %b) nounwind {115; CHECK-LABEL: test9:116; CHECK: # %bb.0:117; CHECK-NEXT: movq %rsi, %rax118; CHECK-NEXT: cmpq %rsi, %rdi119; CHECK-NEXT: adcq $0, %rax120; CHECK-NEXT: retq121 %cmp = icmp ult i64 %a, %b122 %conv = sext i1 %cmp to i64123 %sub = sub i64 %b, %conv124 ret i64 %sub125}126 127