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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=alderlake -mattr=+false-deps-perm -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=ENABLE,ENABLE-ADL3; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=+false-deps-perm -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=ENABLE,ENABLE-SPR4; RUN: llc -verify-machineinstrs -mcpu=alderlake -mattr=-false-deps-perm -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=DISABLE,DISABLE-ADL5; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=-false-deps-perm -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=DISABLE,DISABLE-SPR6 7define <8 x i32> @permd(<8 x i32> %a0, <8 x i32> %a1) {8; ENABLE-ADL-LABEL: permd:9; ENABLE-ADL: # %bb.0:10; ENABLE-ADL-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill11; ENABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill12; ENABLE-ADL-NEXT: #APP13; ENABLE-ADL-NEXT: nop14; ENABLE-ADL-NEXT: #NO_APP15; ENABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload16; ENABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload17; ENABLE-ADL-NEXT: vxorps %xmm0, %xmm0, %xmm018; ENABLE-ADL-NEXT: vpermd %ymm2, %ymm1, %ymm019; ENABLE-ADL-NEXT: vpaddd %ymm1, %ymm2, %ymm120; ENABLE-ADL-NEXT: vpaddd %ymm1, %ymm0, %ymm021; ENABLE-ADL-NEXT: retq22;23; ENABLE-SPR-LABEL: permd:24; ENABLE-SPR: # %bb.0:25; ENABLE-SPR-NEXT: vmovdqa64 %ymm1, %ymm1626; ENABLE-SPR-NEXT: vmovdqa64 %ymm0, %ymm1727; ENABLE-SPR-NEXT: #APP28; ENABLE-SPR-NEXT: nop29; ENABLE-SPR-NEXT: #NO_APP30; ENABLE-SPR-NEXT: vxorps %xmm0, %xmm0, %xmm031; ENABLE-SPR-NEXT: vpermd %ymm17, %ymm16, %ymm032; ENABLE-SPR-NEXT: vpaddd %ymm16, %ymm17, %ymm133; ENABLE-SPR-NEXT: vpaddd %ymm1, %ymm0, %ymm034; ENABLE-SPR-NEXT: retq35;36; DISABLE-ADL-LABEL: permd:37; DISABLE-ADL: # %bb.0:38; DISABLE-ADL-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill39; DISABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill40; DISABLE-ADL-NEXT: #APP41; DISABLE-ADL-NEXT: nop42; DISABLE-ADL-NEXT: #NO_APP43; DISABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload44; DISABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload45; DISABLE-ADL-NEXT: vpermd %ymm2, %ymm1, %ymm046; DISABLE-ADL-NEXT: vpaddd %ymm1, %ymm2, %ymm147; DISABLE-ADL-NEXT: vpaddd %ymm1, %ymm0, %ymm048; DISABLE-ADL-NEXT: retq49;50; DISABLE-SPR-LABEL: permd:51; DISABLE-SPR: # %bb.0:52; DISABLE-SPR-NEXT: vmovdqa64 %ymm1, %ymm1653; DISABLE-SPR-NEXT: vmovdqa64 %ymm0, %ymm1754; DISABLE-SPR-NEXT: #APP55; DISABLE-SPR-NEXT: nop56; DISABLE-SPR-NEXT: #NO_APP57; DISABLE-SPR-NEXT: vpermd %ymm17, %ymm16, %ymm058; DISABLE-SPR-NEXT: vpaddd %ymm16, %ymm17, %ymm159; DISABLE-SPR-NEXT: vpaddd %ymm1, %ymm0, %ymm060; DISABLE-SPR-NEXT: retq61 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()62 %2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1)63 %3 = add <8 x i32> %a0, %a164 %res = add <8 x i32> %2, %365 ret <8 x i32> %res66}67 68define <8 x i32> @permd_mem(ptr %p0, <8 x i32> %a1) {69; ENABLE-ADL-LABEL: permd_mem:70; ENABLE-ADL: # %bb.0:71; ENABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill72; ENABLE-ADL-NEXT: #APP73; ENABLE-ADL-NEXT: nop74; ENABLE-ADL-NEXT: #NO_APP75; ENABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload76; ENABLE-ADL-NEXT: vxorps %xmm0, %xmm0, %xmm077; ENABLE-ADL-NEXT: vpermd (%rdi), %ymm1, %ymm078; ENABLE-ADL-NEXT: vpaddd %ymm1, %ymm0, %ymm079; ENABLE-ADL-NEXT: retq80;81; ENABLE-SPR-LABEL: permd_mem:82; ENABLE-SPR: # %bb.0:83; ENABLE-SPR-NEXT: vmovdqa64 %ymm0, %ymm1684; ENABLE-SPR-NEXT: #APP85; ENABLE-SPR-NEXT: nop86; ENABLE-SPR-NEXT: #NO_APP87; ENABLE-SPR-NEXT: vxorps %xmm0, %xmm0, %xmm088; ENABLE-SPR-NEXT: vpermd (%rdi), %ymm16, %ymm089; ENABLE-SPR-NEXT: vpaddd %ymm16, %ymm0, %ymm090; ENABLE-SPR-NEXT: retq91;92; DISABLE-ADL-LABEL: permd_mem:93; DISABLE-ADL: # %bb.0:94; DISABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill95; DISABLE-ADL-NEXT: #APP96; DISABLE-ADL-NEXT: nop97; DISABLE-ADL-NEXT: #NO_APP98; DISABLE-ADL-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload99; DISABLE-ADL-NEXT: vpermd (%rdi), %ymm1, %ymm0100; DISABLE-ADL-NEXT: vpaddd %ymm1, %ymm0, %ymm0101; DISABLE-ADL-NEXT: retq102;103; DISABLE-SPR-LABEL: permd_mem:104; DISABLE-SPR: # %bb.0:105; DISABLE-SPR-NEXT: vmovdqa64 %ymm0, %ymm16106; DISABLE-SPR-NEXT: #APP107; DISABLE-SPR-NEXT: nop108; DISABLE-SPR-NEXT: #NO_APP109; DISABLE-SPR-NEXT: vpermd (%rdi), %ymm16, %ymm0110; DISABLE-SPR-NEXT: vpaddd %ymm16, %ymm0, %ymm0111; DISABLE-SPR-NEXT: retq112 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()113 %a0 = load <8 x i32>, ptr %p0, align 64114 %2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1)115 %res = add <8 x i32> %2, %a1116 ret <8 x i32> %res117}118 119declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly120 121define <4 x i64> @permq(<4 x i64> %a0) {122; ENABLE-LABEL: permq:123; ENABLE: # %bb.0:124; ENABLE-NEXT: #APP125; ENABLE-NEXT: nop126; ENABLE-NEXT: #NO_APP127; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1128; ENABLE-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,2,1,0]129; ENABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0130; ENABLE-NEXT: retq131;132; DISABLE-LABEL: permq:133; DISABLE: # %bb.0:134; DISABLE-NEXT: #APP135; DISABLE-NEXT: nop136; DISABLE-NEXT: #NO_APP137; DISABLE-NEXT: vpermq {{.*#+}} ymm1 = ymm0[1,2,1,0]138; DISABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0139; DISABLE-NEXT: retq140 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()141 %2 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>142 %res = add <4 x i64> %2, %a0143 ret <4 x i64> %res144}145 146define <4 x i64> @permq_mem(ptr %p0) {147; ENABLE-LABEL: permq_mem:148; ENABLE: # %bb.0:149; ENABLE-NEXT: #APP150; ENABLE-NEXT: nop151; ENABLE-NEXT: #NO_APP152; ENABLE-NEXT: vxorps %xmm0, %xmm0, %xmm0153; ENABLE-NEXT: vpermpd {{.*#+}} ymm0 = mem[1,2,1,0]154; ENABLE-NEXT: retq155;156; DISABLE-LABEL: permq_mem:157; DISABLE: # %bb.0:158; DISABLE-NEXT: #APP159; DISABLE-NEXT: nop160; DISABLE-NEXT: #NO_APP161; DISABLE-NEXT: vpermpd {{.*#+}} ymm0 = mem[1,2,1,0]162; DISABLE-NEXT: retq163 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()164 %a0 = load <4 x i64>, ptr %p0, align 64165 %2 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>166 ret <4 x i64> %2167}168 169define <8 x float> @permps(<8 x float> %a0, <8 x i32> %a1) {170; ENABLE-ADL-LABEL: permps:171; ENABLE-ADL: # %bb.0:172; ENABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill173; ENABLE-ADL-NEXT: #APP174; ENABLE-ADL-NEXT: nop175; ENABLE-ADL-NEXT: #NO_APP176; ENABLE-ADL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload177; ENABLE-ADL-NEXT: vxorps %xmm1, %xmm1, %xmm1178; ENABLE-ADL-NEXT: vpermps %ymm2, %ymm0, %ymm1179; ENABLE-ADL-NEXT: vcvtdq2ps %ymm0, %ymm0180; ENABLE-ADL-NEXT: vaddps %ymm2, %ymm0, %ymm0181; ENABLE-ADL-NEXT: vaddps %ymm0, %ymm1, %ymm0182; ENABLE-ADL-NEXT: retq183;184; ENABLE-SPR-LABEL: permps:185; ENABLE-SPR: # %bb.0:186; ENABLE-SPR-NEXT: vmovaps %ymm0, %ymm16187; ENABLE-SPR-NEXT: #APP188; ENABLE-SPR-NEXT: nop189; ENABLE-SPR-NEXT: #NO_APP190; ENABLE-SPR-NEXT: vxorps %xmm1, %xmm1, %xmm1191; ENABLE-SPR-NEXT: vpermps %ymm16, %ymm0, %ymm1192; ENABLE-SPR-NEXT: vcvtdq2ps %ymm0, %ymm0193; ENABLE-SPR-NEXT: vaddps %ymm16, %ymm0, %ymm0194; ENABLE-SPR-NEXT: vaddps %ymm0, %ymm1, %ymm0195; ENABLE-SPR-NEXT: retq196;197; DISABLE-ADL-LABEL: permps:198; DISABLE-ADL: # %bb.0:199; DISABLE-ADL-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill200; DISABLE-ADL-NEXT: #APP201; DISABLE-ADL-NEXT: nop202; DISABLE-ADL-NEXT: #NO_APP203; DISABLE-ADL-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload204; DISABLE-ADL-NEXT: vpermps %ymm2, %ymm0, %ymm1205; DISABLE-ADL-NEXT: vcvtdq2ps %ymm0, %ymm0206; DISABLE-ADL-NEXT: vaddps %ymm2, %ymm0, %ymm0207; DISABLE-ADL-NEXT: vaddps %ymm0, %ymm1, %ymm0208; DISABLE-ADL-NEXT: retq209;210; DISABLE-SPR-LABEL: permps:211; DISABLE-SPR: # %bb.0:212; DISABLE-SPR-NEXT: vmovaps %ymm0, %ymm16213; DISABLE-SPR-NEXT: #APP214; DISABLE-SPR-NEXT: nop215; DISABLE-SPR-NEXT: #NO_APP216; DISABLE-SPR-NEXT: vpermps %ymm16, %ymm0, %ymm1217; DISABLE-SPR-NEXT: vcvtdq2ps %ymm0, %ymm0218; DISABLE-SPR-NEXT: vaddps %ymm16, %ymm0, %ymm0219; DISABLE-SPR-NEXT: vaddps %ymm0, %ymm1, %ymm0220; DISABLE-SPR-NEXT: retq221 %1 = tail call <8 x i32> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()222 %2 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %1)223 %t = sitofp <8 x i32> %1 to <8 x float>224 %3 = fadd <8 x float> %t, %a0225 %res = fadd <8 x float> %2, %3226 ret <8 x float> %res227}228 229define <8 x float> @permps_mem(ptr %p0, <8 x i32> %a1) {230; ENABLE-LABEL: permps_mem:231; ENABLE: # %bb.0:232; ENABLE-NEXT: #APP233; ENABLE-NEXT: nop234; ENABLE-NEXT: #NO_APP235; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1236; ENABLE-NEXT: vpermps (%rdi), %ymm0, %ymm1237; ENABLE-NEXT: vcvtdq2ps %ymm0, %ymm0238; ENABLE-NEXT: vaddps %ymm0, %ymm1, %ymm0239; ENABLE-NEXT: retq240;241; DISABLE-LABEL: permps_mem:242; DISABLE: # %bb.0:243; DISABLE-NEXT: #APP244; DISABLE-NEXT: nop245; DISABLE-NEXT: #NO_APP246; DISABLE-NEXT: vpermps (%rdi), %ymm0, %ymm1247; DISABLE-NEXT: vcvtdq2ps %ymm0, %ymm0248; DISABLE-NEXT: vaddps %ymm0, %ymm1, %ymm0249; DISABLE-NEXT: retq250 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()251 %a0 = load <8 x float>, ptr %p0, align 64252 %2 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1)253 %t = sitofp <8 x i32> %a1 to <8 x float>254 %res = fadd <8 x float> %2, %t255 ret <8 x float> %res256}257 258declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) nounwind readonly259 260define <4 x double> @permpd(<4 x double> %a0) {261; ENABLE-LABEL: permpd:262; ENABLE: # %bb.0:263; ENABLE-NEXT: #APP264; ENABLE-NEXT: nop265; ENABLE-NEXT: #NO_APP266; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1267; ENABLE-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[1,2,1,0]268; ENABLE-NEXT: vaddpd %ymm0, %ymm1, %ymm0269; ENABLE-NEXT: retq270;271; DISABLE-LABEL: permpd:272; DISABLE: # %bb.0:273; DISABLE-NEXT: #APP274; DISABLE-NEXT: nop275; DISABLE-NEXT: #NO_APP276; DISABLE-NEXT: vpermpd {{.*#+}} ymm1 = ymm0[1,2,1,0]277; DISABLE-NEXT: vaddpd %ymm0, %ymm1, %ymm0278; DISABLE-NEXT: retq279 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()280 %2 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>281 %res = fadd <4 x double> %2, %a0282 ret <4 x double> %res283}284 285define <4 x double> @permpd_mem(ptr %p0) {286; ENABLE-LABEL: permpd_mem:287; ENABLE: # %bb.0:288; ENABLE-NEXT: #APP289; ENABLE-NEXT: nop290; ENABLE-NEXT: #NO_APP291; ENABLE-NEXT: vxorps %xmm0, %xmm0, %xmm0292; ENABLE-NEXT: vpermpd {{.*#+}} ymm0 = mem[1,2,1,0]293; ENABLE-NEXT: retq294;295; DISABLE-LABEL: permpd_mem:296; DISABLE: # %bb.0:297; DISABLE-NEXT: #APP298; DISABLE-NEXT: nop299; DISABLE-NEXT: #NO_APP300; DISABLE-NEXT: vpermpd {{.*#+}} ymm0 = mem[1,2,1,0]301; DISABLE-NEXT: retq302 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()303 %a0 = load <4 x double>, ptr %p0, align 64304 %2 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 0>305 ret <4 x double> %2306}307