364 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=+false-deps-mullq -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=ENABLE3; RUN: llc -verify-machineinstrs -mcpu=sapphirerapids -mattr=-false-deps-mullq -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefixes=DISABLE4 5define <2 x i64> @pmullq_128(<2 x i64> %a0, <2 x i64> %a1) {6; ENABLE-LABEL: pmullq_128:7; ENABLE: # %bb.0:8; ENABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill9; ENABLE-NEXT: #APP10; ENABLE-NEXT: nop11; ENABLE-NEXT: #NO_APP12; ENABLE-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload13; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm114; ENABLE-NEXT: vpmullq %xmm2, %xmm0, %xmm115; ENABLE-NEXT: vpaddq %xmm2, %xmm0, %xmm016; ENABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm017; ENABLE-NEXT: retq18;19; DISABLE-LABEL: pmullq_128:20; DISABLE: # %bb.0:21; DISABLE-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill22; DISABLE-NEXT: #APP23; DISABLE-NEXT: nop24; DISABLE-NEXT: #NO_APP25; DISABLE-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload26; DISABLE-NEXT: vpmullq %xmm2, %xmm0, %xmm127; DISABLE-NEXT: vpaddq %xmm2, %xmm0, %xmm028; DISABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm029; DISABLE-NEXT: retq30 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()31 %2 = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> undef, i8 -1)32 %3 = add <2 x i64> %a0, %a133 %res = add <2 x i64> %2, %334 ret <2 x i64> %res35}36 37define <2 x i64> @pmullq_mem_128(<2 x i64> %a0, ptr %p1) {38; ENABLE-LABEL: pmullq_mem_128:39; ENABLE: # %bb.0:40; ENABLE-NEXT: #APP41; ENABLE-NEXT: nop42; ENABLE-NEXT: #NO_APP43; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm144; ENABLE-NEXT: vpmullq (%rdi), %xmm0, %xmm145; ENABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm046; ENABLE-NEXT: retq47;48; DISABLE-LABEL: pmullq_mem_128:49; DISABLE: # %bb.0:50; DISABLE-NEXT: #APP51; DISABLE-NEXT: nop52; DISABLE-NEXT: #NO_APP53; DISABLE-NEXT: vpmullq (%rdi), %xmm0, %xmm154; DISABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm055; DISABLE-NEXT: retq56 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()57 %a1 = load <2 x i64>, ptr %p1, align 6458 %2 = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> undef, i8 -1)59 %res = add <2 x i64> %2, %a060 ret <2 x i64> %res61}62 63define <2 x i64> @pmullq_broadcast_128(<2 x i64> %a0, ptr %p1) {64; ENABLE-LABEL: pmullq_broadcast_128:65; ENABLE: # %bb.0:66; ENABLE-NEXT: #APP67; ENABLE-NEXT: nop68; ENABLE-NEXT: #NO_APP69; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm170; ENABLE-NEXT: vpmullq (%rdi){1to2}, %xmm0, %xmm171; ENABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm072; ENABLE-NEXT: retq73;74; DISABLE-LABEL: pmullq_broadcast_128:75; DISABLE: # %bb.0:76; DISABLE-NEXT: #APP77; DISABLE-NEXT: nop78; DISABLE-NEXT: #NO_APP79; DISABLE-NEXT: vpmullq (%rdi){1to2}, %xmm0, %xmm180; DISABLE-NEXT: vpaddq %xmm0, %xmm1, %xmm081; DISABLE-NEXT: retq82 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()83 %v1 = load i64, ptr %p1, align 484 %t0 = insertelement <2 x i64> undef, i64 %v1, i64 085 %a1 = shufflevector <2 x i64> %t0, <2 x i64> undef, <2 x i32> zeroinitializer86 %2 = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> undef, i8 -1)87 %res = add <2 x i64> %2, %a088 ret <2 x i64> %res89}90 91define <2 x i64> @pmullq_maskz_128(<2 x i64> %a0, <2 x i64> %a1, ptr %pmask) {92; ENABLE-LABEL: pmullq_maskz_128:93; ENABLE: # %bb.0:94; ENABLE-NEXT: vpmullq %xmm1, %xmm0, %xmm295; ENABLE-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill96; ENABLE-NEXT: #APP97; ENABLE-NEXT: nop98; ENABLE-NEXT: #NO_APP99; ENABLE-NEXT: kmovb (%rdi), %k1100; ENABLE-NEXT: vpaddq %xmm1, %xmm0, %xmm0101; ENABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 {%k1} # 16-byte Folded Reload102; ENABLE-NEXT: retq103;104; DISABLE-LABEL: pmullq_maskz_128:105; DISABLE: # %bb.0:106; DISABLE-NEXT: vpmullq %xmm1, %xmm0, %xmm2107; DISABLE-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill108; DISABLE-NEXT: #APP109; DISABLE-NEXT: nop110; DISABLE-NEXT: #NO_APP111; DISABLE-NEXT: kmovb (%rdi), %k1112; DISABLE-NEXT: vpaddq %xmm1, %xmm0, %xmm0113; DISABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 {%k1} # 16-byte Folded Reload114; DISABLE-NEXT: retq115 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()116 %mask = load i8, ptr %pmask117 %2 = call <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> zeroinitializer, i8 %mask)118 %3 = add <2 x i64> %a0, %a1119 %res = add <2 x i64> %2, %3120 ret <2 x i64> %res121}122 123declare <2 x i64> @llvm.x86.avx512.mask.pmull.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)124 125define <4 x i64> @pmullq_256(<4 x i64> %a0, <4 x i64> %a1) {126; ENABLE-LABEL: pmullq_256:127; ENABLE: # %bb.0:128; ENABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill129; ENABLE-NEXT: #APP130; ENABLE-NEXT: nop131; ENABLE-NEXT: #NO_APP132; ENABLE-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload133; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1134; ENABLE-NEXT: vpmullq %ymm2, %ymm0, %ymm1135; ENABLE-NEXT: vpaddq %ymm2, %ymm0, %ymm0136; ENABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0137; ENABLE-NEXT: retq138;139; DISABLE-LABEL: pmullq_256:140; DISABLE: # %bb.0:141; DISABLE-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill142; DISABLE-NEXT: #APP143; DISABLE-NEXT: nop144; DISABLE-NEXT: #NO_APP145; DISABLE-NEXT: vmovdqu {{[-0-9]+}}(%r{{[sb]}}p), %ymm2 # 32-byte Reload146; DISABLE-NEXT: vpmullq %ymm2, %ymm0, %ymm1147; DISABLE-NEXT: vpaddq %ymm2, %ymm0, %ymm0148; DISABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0149; DISABLE-NEXT: retq150 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()151 %2 = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> undef, i8 -1)152 %3 = add <4 x i64> %a0, %a1153 %res = add <4 x i64> %2, %3154 ret <4 x i64> %res155}156 157define <4 x i64> @pmullq_mem_256(<4 x i64> %a0, ptr %p1) {158; ENABLE-LABEL: pmullq_mem_256:159; ENABLE: # %bb.0:160; ENABLE-NEXT: #APP161; ENABLE-NEXT: nop162; ENABLE-NEXT: #NO_APP163; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1164; ENABLE-NEXT: vpmullq (%rdi), %ymm0, %ymm1165; ENABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0166; ENABLE-NEXT: retq167;168; DISABLE-LABEL: pmullq_mem_256:169; DISABLE: # %bb.0:170; DISABLE-NEXT: #APP171; DISABLE-NEXT: nop172; DISABLE-NEXT: #NO_APP173; DISABLE-NEXT: vpmullq (%rdi), %ymm0, %ymm1174; DISABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0175; DISABLE-NEXT: retq176 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()177 %a1 = load <4 x i64>, ptr %p1, align 64178 %2 = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> undef, i8 -1)179 %res = add <4 x i64> %2, %a0180 ret <4 x i64> %res181}182 183define <4 x i64> @pmullq_broadcast_256(<4 x i64> %a0, ptr %p1) {184; ENABLE-LABEL: pmullq_broadcast_256:185; ENABLE: # %bb.0:186; ENABLE-NEXT: #APP187; ENABLE-NEXT: nop188; ENABLE-NEXT: #NO_APP189; ENABLE-NEXT: vxorps %xmm1, %xmm1, %xmm1190; ENABLE-NEXT: vpmullq (%rdi){1to4}, %ymm0, %ymm1191; ENABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0192; ENABLE-NEXT: retq193;194; DISABLE-LABEL: pmullq_broadcast_256:195; DISABLE: # %bb.0:196; DISABLE-NEXT: #APP197; DISABLE-NEXT: nop198; DISABLE-NEXT: #NO_APP199; DISABLE-NEXT: vpmullq (%rdi){1to4}, %ymm0, %ymm1200; DISABLE-NEXT: vpaddq %ymm0, %ymm1, %ymm0201; DISABLE-NEXT: retq202 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()203 %v1 = load i64, ptr %p1, align 4204 %t0 = insertelement <4 x i64> undef, i64 %v1, i64 0205 %a1 = shufflevector <4 x i64> %t0, <4 x i64> undef, <4 x i32> zeroinitializer206 %2 = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> undef, i8 -1)207 %res = add <4 x i64> %2, %a0208 ret <4 x i64> %res209}210 211define <4 x i64> @pmullq_maskz_256(<4 x i64> %a0, <4 x i64> %a1, ptr %pmask) {212; ENABLE-LABEL: pmullq_maskz_256:213; ENABLE: # %bb.0:214; ENABLE-NEXT: vpmullq %ymm1, %ymm0, %ymm2215; ENABLE-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill216; ENABLE-NEXT: #APP217; ENABLE-NEXT: nop218; ENABLE-NEXT: #NO_APP219; ENABLE-NEXT: kmovb (%rdi), %k1220; ENABLE-NEXT: vpaddq %ymm1, %ymm0, %ymm0221; ENABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 {%k1} # 32-byte Folded Reload222; ENABLE-NEXT: retq223;224; DISABLE-LABEL: pmullq_maskz_256:225; DISABLE: # %bb.0:226; DISABLE-NEXT: vpmullq %ymm1, %ymm0, %ymm2227; DISABLE-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill228; DISABLE-NEXT: #APP229; DISABLE-NEXT: nop230; DISABLE-NEXT: #NO_APP231; DISABLE-NEXT: kmovb (%rdi), %k1232; DISABLE-NEXT: vpaddq %ymm1, %ymm0, %ymm0233; DISABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 {%k1} # 32-byte Folded Reload234; DISABLE-NEXT: retq235 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()236 %mask = load i8, ptr %pmask237 %2 = call <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> zeroinitializer, i8 %mask)238 %3 = add <4 x i64> %a0, %a1239 %res = add <4 x i64> %2, %3240 ret <4 x i64> %res241}242 243declare <4 x i64> @llvm.x86.avx512.mask.pmull.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)244 245define <8 x i64> @pmullq_512(<8 x i64> %a0, <8 x i64> %a1) {246; ENABLE-LABEL: pmullq_512:247; ENABLE: # %bb.0:248; ENABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill249; ENABLE-NEXT: #APP250; ENABLE-NEXT: nop251; ENABLE-NEXT: #NO_APP252; ENABLE-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload253; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm1254; ENABLE-NEXT: vpmullq %zmm2, %zmm0, %zmm1255; ENABLE-NEXT: vpaddq %zmm2, %zmm0, %zmm0256; ENABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0257; ENABLE-NEXT: retq258;259; DISABLE-LABEL: pmullq_512:260; DISABLE: # %bb.0:261; DISABLE-NEXT: vmovups %zmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill262; DISABLE-NEXT: #APP263; DISABLE-NEXT: nop264; DISABLE-NEXT: #NO_APP265; DISABLE-NEXT: vmovdqu64 {{[-0-9]+}}(%r{{[sb]}}p), %zmm2 # 64-byte Reload266; DISABLE-NEXT: vpmullq %zmm2, %zmm0, %zmm1267; DISABLE-NEXT: vpaddq %zmm2, %zmm0, %zmm0268; DISABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0269; DISABLE-NEXT: retq270 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()271 %2 = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> undef, i8 -1)272 %3 = add <8 x i64> %a0, %a1273 %res = add <8 x i64> %2, %3274 ret <8 x i64> %res275}276 277define <8 x i64> @pmullq_mem_512(<8 x i64> %a0, ptr %p1) {278; ENABLE-LABEL: pmullq_mem_512:279; ENABLE: # %bb.0:280; ENABLE-NEXT: #APP281; ENABLE-NEXT: nop282; ENABLE-NEXT: #NO_APP283; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm1284; ENABLE-NEXT: vpmullq (%rdi), %zmm0, %zmm1285; ENABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0286; ENABLE-NEXT: retq287;288; DISABLE-LABEL: pmullq_mem_512:289; DISABLE: # %bb.0:290; DISABLE-NEXT: #APP291; DISABLE-NEXT: nop292; DISABLE-NEXT: #NO_APP293; DISABLE-NEXT: vpmullq (%rdi), %zmm0, %zmm1294; DISABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0295; DISABLE-NEXT: retq296 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()297 %a1 = load <8 x i64>, ptr %p1, align 64298 %2 = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> undef, i8 -1)299 %res = add <8 x i64> %2, %a0300 ret <8 x i64> %res301}302 303define <8 x i64> @pmullq_broadcast_512(<8 x i64> %a0, ptr %p1) {304; ENABLE-LABEL: pmullq_broadcast_512:305; ENABLE: # %bb.0:306; ENABLE-NEXT: #APP307; ENABLE-NEXT: nop308; ENABLE-NEXT: #NO_APP309; ENABLE-NEXT: vpxor %xmm1, %xmm1, %xmm1310; ENABLE-NEXT: vpmullq (%rdi){1to8}, %zmm0, %zmm1311; ENABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0312; ENABLE-NEXT: retq313;314; DISABLE-LABEL: pmullq_broadcast_512:315; DISABLE: # %bb.0:316; DISABLE-NEXT: #APP317; DISABLE-NEXT: nop318; DISABLE-NEXT: #NO_APP319; DISABLE-NEXT: vpmullq (%rdi){1to8}, %zmm0, %zmm1320; DISABLE-NEXT: vpaddq %zmm0, %zmm1, %zmm0321; DISABLE-NEXT: retq322 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()323 %v1 = load i64, ptr %p1, align 4324 %t0 = insertelement <8 x i64> undef, i64 %v1, i64 0325 %a1 = shufflevector <8 x i64> %t0, <8 x i64> undef, <8 x i32> zeroinitializer326 %2 = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> undef, i8 -1)327 %res = add <8 x i64> %2, %a0328 ret <8 x i64> %res329}330 331define <8 x i64> @pmullq_maskz_512(<8 x i64> %a0, <8 x i64> %a1, ptr %pmask) {332; ENABLE-LABEL: pmullq_maskz_512:333; ENABLE: # %bb.0:334; ENABLE-NEXT: vpmullq %zmm1, %zmm0, %zmm2335; ENABLE-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill336; ENABLE-NEXT: #APP337; ENABLE-NEXT: nop338; ENABLE-NEXT: #NO_APP339; ENABLE-NEXT: kmovb (%rdi), %k1340; ENABLE-NEXT: vpaddq %zmm1, %zmm0, %zmm0341; ENABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload342; ENABLE-NEXT: retq343;344; DISABLE-LABEL: pmullq_maskz_512:345; DISABLE: # %bb.0:346; DISABLE-NEXT: vpmullq %zmm1, %zmm0, %zmm2347; DISABLE-NEXT: vmovdqu64 %zmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 64-byte Spill348; DISABLE-NEXT: #APP349; DISABLE-NEXT: nop350; DISABLE-NEXT: #NO_APP351; DISABLE-NEXT: kmovb (%rdi), %k1352; DISABLE-NEXT: vpaddq %zmm1, %zmm0, %zmm0353; DISABLE-NEXT: vpaddq {{[-0-9]+}}(%r{{[sb]}}p), %zmm0, %zmm0 {%k1} # 64-byte Folded Reload354; DISABLE-NEXT: retq355 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()356 %mask = load i8, ptr %pmask357 %2 = call <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a0, <8 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)358 %3 = add <8 x i64> %a0, %a1359 %res = add <8 x i64> %2, %3360 ret <8 x i64> %res361}362 363declare <8 x i64> @llvm.x86.avx512.mask.pmull.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)364