34 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=i686-pc-windows-msvc -mcpu=corei7-avx | FileCheck %s3 4define void @PR111170(<16 x i32> %x_load, ptr %offsetsPtr.i) {5; CHECK-LABEL: PR111170:6; CHECK: # %bb.0:7; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax8; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [2.80259693E-44,2.80259693E-44,2.80259693E-44,2.80259693E-44]9; CHECK-NEXT: vpmulld %xmm2, %xmm1, %xmm310; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm111; CHECK-NEXT: vpmulld %xmm2, %xmm1, %xmm112; CHECK-NEXT: vpmulld %xmm2, %xmm0, %xmm413; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm014; CHECK-NEXT: vpmulld %xmm2, %xmm0, %xmm015; CHECK-NEXT: vmovdqu %xmm0, 16(%eax)16; CHECK-NEXT: vmovdqu %xmm4, (%eax)17; CHECK-NEXT: vmovdqu %xmm1, 48(%eax)18; CHECK-NEXT: vmovdqu %xmm3, 32(%eax)19; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm020; CHECK-NEXT: vmovdqu %xmm0, 1621; CHECK-NEXT: vmovdqu %xmm0, 022; CHECK-NEXT: vmovdqu %xmm0, 4823; CHECK-NEXT: vmovdqu %xmm0, 3224; CHECK-NEXT: vzeroupper25; CHECK-NEXT: retl26 %mul__x_load = mul <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20, i32 20>, %x_load27 store <16 x i32> %mul__x_load, ptr %offsetsPtr.i, align 428 %blend1.i12.i = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> zeroinitializer, <8 x float> <float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000, float 0x36E4000000000000>, <8 x float> zeroinitializer)29 %blend.i13.i = shufflevector <8 x float> zeroinitializer, <8 x float> %blend1.i12.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>30 %blendAsInt.i14.i = bitcast <16 x float> %blend.i13.i to <16 x i32>31 store <16 x i32> %blendAsInt.i14.i, ptr null, align 432 ret void33}34