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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=core-avx-i | FileCheck %s --check-prefix=AVX4 5define <2 x double> @v2f2d_ext_vec(<2 x float> %v1) nounwind {6; SSE-LABEL: v2f2d_ext_vec:7; SSE: # %bb.0: # %entry8; SSE-NEXT: cvtps2pd %xmm0, %xmm09; SSE-NEXT: retq10;11; AVX-LABEL: v2f2d_ext_vec:12; AVX: # %bb.0: # %entry13; AVX-NEXT: vcvtps2pd %xmm0, %xmm014; AVX-NEXT: retq15entry:16 %f1 = fpext <2 x float> %v1 to <2 x double>17 ret <2 x double> %f118}19 20define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {21; SSE-LABEL: v3f2d_ext_vec:22; SSE: # %bb.0: # %entry23; SSE-NEXT: cvtps2pd %xmm0, %xmm224; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]25; SSE-NEXT: cvtps2pd %xmm0, %xmm026; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)27; SSE-NEXT: movaps %xmm2, %xmm128; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]29; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)30; SSE-NEXT: movaps %xmm2, %xmm031; SSE-NEXT: retq32;33; AVX-LABEL: v3f2d_ext_vec:34; AVX: # %bb.0: # %entry35; AVX-NEXT: vcvtps2pd %xmm0, %ymm036; AVX-NEXT: retq37entry:38 %f1 = fpext <3 x float> %v1 to <3 x double>39 ret <3 x double> %f140}41 42define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind {43; SSE-LABEL: v4f2d_ext_vec:44; SSE: # %bb.0: # %entry45; SSE-NEXT: cvtps2pd %xmm0, %xmm246; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]47; SSE-NEXT: cvtps2pd %xmm0, %xmm148; SSE-NEXT: movaps %xmm2, %xmm049; SSE-NEXT: retq50;51; AVX-LABEL: v4f2d_ext_vec:52; AVX: # %bb.0: # %entry53; AVX-NEXT: vcvtps2pd %xmm0, %ymm054; AVX-NEXT: retq55entry:56 %f1 = fpext <4 x float> %v1 to <4 x double>57 ret <4 x double> %f158}59 60define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind {61; SSE-LABEL: v8f2d_ext_vec:62; SSE: # %bb.0: # %entry63; SSE-NEXT: cvtps2pd %xmm0, %xmm564; SSE-NEXT: cvtps2pd %xmm1, %xmm265; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]66; SSE-NEXT: cvtps2pd %xmm0, %xmm467; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]68; SSE-NEXT: cvtps2pd %xmm1, %xmm369; SSE-NEXT: movaps %xmm5, %xmm070; SSE-NEXT: movaps %xmm4, %xmm171; SSE-NEXT: retq72;73; AVX-LABEL: v8f2d_ext_vec:74; AVX: # %bb.0: # %entry75; AVX-NEXT: vcvtps2pd %xmm0, %ymm276; AVX-NEXT: vextractf128 $1, %ymm0, %xmm077; AVX-NEXT: vcvtps2pd %xmm0, %ymm178; AVX-NEXT: vmovaps %ymm2, %ymm079; AVX-NEXT: retq80entry:81 %f1 = fpext <8 x float> %v1 to <8 x double>82 ret <8 x double> %f183}84 85define void @test_vector_creation() nounwind {86; SSE-LABEL: test_vector_creation:87; SSE: # %bb.0:88; SSE-NEXT: xorps %xmm0, %xmm089; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]90; SSE-NEXT: movaps %xmm0, (%rax)91; SSE-NEXT: retq92;93; AVX-LABEL: test_vector_creation:94; AVX: # %bb.0:95; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm096; AVX-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]97; AVX-NEXT: vmovaps %xmm0, (%rax)98; AVX-NEXT: retq99 %1 = insertelement <4 x double> undef, double 0.000000e+00, i32 2100 %2 = load double, ptr addrspace(1) null101 %3 = insertelement <4 x double> %1, double %2, i32 3102 store <4 x double> %3, ptr undef103 ret void104}105