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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -verify-machineinstrs | FileCheck %s3 4; We were miscompiling this and using %ax instead of %cx in the movw5; in the following sequence:6; movswl %cx, %ecx7; movw %cx, (%rsi)8; movslq %ecx, %rcx9;10; We can't produce the above sequence without special SD-level11; heuristics. Now we produce this:12 13define i32 @f(i1 %foo, ptr %tm_year2, ptr %bar, i16 %zed, i32 %zed2) {14; CHECK-LABEL: f:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: movl $-1, %eax17; CHECK-NEXT: testb $1, %dil18; CHECK-NEXT: jne .LBB0_219; CHECK-NEXT: # %bb.1: # %if.end20; CHECK-NEXT: movslq %r8d, %rax21; CHECK-NEXT: imulq $1374389535, %rax, %rcx # imm = 0x51EB851F22; CHECK-NEXT: movq %rcx, %rdi23; CHECK-NEXT: shrq $63, %rdi24; CHECK-NEXT: sarq $37, %rcx25; CHECK-NEXT: addl %edi, %ecx26; CHECK-NEXT: imull $100, %ecx, %ecx27; CHECK-NEXT: subl %ecx, %eax28; CHECK-NEXT: movw %ax, (%rsi)29; CHECK-NEXT: movswq %ax, %rax30; CHECK-NEXT: imulq $1717986919, %rax, %rax # imm = 0x6666666731; CHECK-NEXT: movq %rax, %rcx32; CHECK-NEXT: shrq $63, %rcx33; CHECK-NEXT: shrq $34, %rax34; CHECK-NEXT: addl %ecx, %eax35; CHECK-NEXT: movb %al, (%rdx)36; CHECK-NEXT: xorl %eax, %eax37; CHECK-NEXT: .LBB0_2: # %return38; CHECK-NEXT: retq39entry:40 br i1 %foo, label %return, label %if.end41 42if.end:43 %rem = srem i32 %zed2, 10044 %conv3 = trunc i32 %rem to i1645 store i16 %conv3, ptr %tm_year246 %sext = shl i32 %rem, 1647 %conv5 = ashr exact i32 %sext, 1648 %div = sdiv i32 %conv5, 1049 %conv6 = trunc i32 %div to i850 store i8 %conv6, ptr %bar51 br label %return52 53return:54 %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ]55 ret i32 %retval.056}57