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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s3 4define <4 x i3> @test1(ptr %in) nounwind {5; CHECK-LABEL: test1:6; CHECK: # %bb.0:7; CHECK-NEXT: movzwl (%rdi), %eax8; CHECK-NEXT: movl %eax, %ecx9; CHECK-NEXT: shrl $3, %ecx10; CHECK-NEXT: andl $7, %ecx11; CHECK-NEXT: movl %eax, %edx12; CHECK-NEXT: andl $7, %edx13; CHECK-NEXT: vmovd %edx, %xmm014; CHECK-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm015; CHECK-NEXT: movl %eax, %ecx16; CHECK-NEXT: shrl $6, %ecx17; CHECK-NEXT: andl $7, %ecx18; CHECK-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm019; CHECK-NEXT: shrl $9, %eax20; CHECK-NEXT: andl $7, %eax21; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm022; CHECK-NEXT: retq23 %ret = load <4 x i3>, ptr %in, align 124 ret <4 x i3> %ret25}26 27define <4 x i1> @test2(ptr %in) nounwind {28; CHECK-LABEL: test2:29; CHECK: # %bb.0:30; CHECK-NEXT: movzbl (%rdi), %eax31; CHECK-NEXT: movl %eax, %ecx32; CHECK-NEXT: shrb %cl33; CHECK-NEXT: andb $1, %cl34; CHECK-NEXT: movl %eax, %edx35; CHECK-NEXT: andb $1, %dl36; CHECK-NEXT: vmovd %edx, %xmm037; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm038; CHECK-NEXT: movl %eax, %ecx39; CHECK-NEXT: shrb $2, %cl40; CHECK-NEXT: andb $1, %cl41; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm042; CHECK-NEXT: shrb $3, %al43; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm044; CHECK-NEXT: retq45 %ret = load <4 x i1>, ptr %in, align 146 ret <4 x i1> %ret47}48 49define <4 x i64> @test3(ptr %in) nounwind {50; CHECK-LABEL: test3:51; CHECK: # %bb.0:52; CHECK-NEXT: movzbl (%rdi), %eax53; CHECK-NEXT: movzbl %al, %ecx54; CHECK-NEXT: shrb %al55; CHECK-NEXT: movzbl %al, %eax56; CHECK-NEXT: andl $1, %eax57; CHECK-NEXT: negl %eax58; CHECK-NEXT: movl %ecx, %edx59; CHECK-NEXT: andl $1, %edx60; CHECK-NEXT: negl %edx61; CHECK-NEXT: vmovd %edx, %xmm062; CHECK-NEXT: vpinsrd $1, %eax, %xmm0, %xmm063; CHECK-NEXT: movl %ecx, %eax64; CHECK-NEXT: shrb $2, %al65; CHECK-NEXT: movzbl %al, %eax66; CHECK-NEXT: andl $1, %eax67; CHECK-NEXT: negl %eax68; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm069; CHECK-NEXT: shrb $3, %cl70; CHECK-NEXT: movzbl %cl, %eax71; CHECK-NEXT: negl %eax72; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm073; CHECK-NEXT: vpmovsxdq %xmm0, %xmm174; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]75; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm076; CHECK-NEXT: retq77 %wide.load35 = load <4 x i1>, ptr %in, align 178 %sext = sext <4 x i1> %wide.load35 to <4 x i64>79 ret <4 x i64> %sext80}81 82define <16 x i4> @test4(ptr %in) nounwind {83; CHECK-LABEL: test4:84; CHECK: # %bb.0:85; CHECK-NEXT: movq (%rdi), %rax86; CHECK-NEXT: movl %eax, %ecx87; CHECK-NEXT: shrl $4, %ecx88; CHECK-NEXT: andl $15, %ecx89; CHECK-NEXT: movl %eax, %edx90; CHECK-NEXT: andl $15, %edx91; CHECK-NEXT: vmovd %edx, %xmm092; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm093; CHECK-NEXT: movl %eax, %ecx94; CHECK-NEXT: shrl $8, %ecx95; CHECK-NEXT: andl $15, %ecx96; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm097; CHECK-NEXT: movl %eax, %ecx98; CHECK-NEXT: shrl $12, %ecx99; CHECK-NEXT: andl $15, %ecx100; CHECK-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0101; CHECK-NEXT: movl %eax, %ecx102; CHECK-NEXT: shrl $16, %ecx103; CHECK-NEXT: andl $15, %ecx104; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0105; CHECK-NEXT: movl %eax, %ecx106; CHECK-NEXT: shrl $20, %ecx107; CHECK-NEXT: andl $15, %ecx108; CHECK-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0109; CHECK-NEXT: movl %eax, %ecx110; CHECK-NEXT: shrl $24, %ecx111; CHECK-NEXT: andl $15, %ecx112; CHECK-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0113; CHECK-NEXT: movl %eax, %ecx114; CHECK-NEXT: shrl $28, %ecx115; CHECK-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0116; CHECK-NEXT: movq %rax, %rcx117; CHECK-NEXT: shrq $32, %rcx118; CHECK-NEXT: andl $15, %ecx119; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0120; CHECK-NEXT: movq %rax, %rcx121; CHECK-NEXT: shrq $36, %rcx122; CHECK-NEXT: andl $15, %ecx123; CHECK-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0124; CHECK-NEXT: movq %rax, %rcx125; CHECK-NEXT: shrq $40, %rcx126; CHECK-NEXT: andl $15, %ecx127; CHECK-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0128; CHECK-NEXT: movq %rax, %rcx129; CHECK-NEXT: shrq $44, %rcx130; CHECK-NEXT: andl $15, %ecx131; CHECK-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0132; CHECK-NEXT: movq %rax, %rcx133; CHECK-NEXT: shrq $48, %rcx134; CHECK-NEXT: andl $15, %ecx135; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0136; CHECK-NEXT: movq %rax, %rcx137; CHECK-NEXT: shrq $52, %rcx138; CHECK-NEXT: andl $15, %ecx139; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0140; CHECK-NEXT: movq %rax, %rcx141; CHECK-NEXT: shrq $56, %rcx142; CHECK-NEXT: andl $15, %ecx143; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0144; CHECK-NEXT: shrq $60, %rax145; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0146; CHECK-NEXT: retq147 %ret = load <16 x i4>, ptr %in, align 1148 ret <16 x i4> %ret149}150