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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=POSTRA3; RUN: llc < %s -mtriple=x86_64-- -mcpu=haswell | FileCheck %s --check-prefixes=NOPOSTRA4; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=NOPOSTRA5 6; Ensure reloads are after narrowed i512 -> i32 store7define i1 @PR166744(ptr %v, i64 %idx, i1 zeroext %b) {8; POSTRA-LABEL: PR166744:9; POSTRA: # %bb.0:10; POSTRA-NEXT: movl $1029, %eax # imm = 0x40511; POSTRA-NEXT: shlxl %esi, %edx, %edx12; POSTRA-NEXT: bextrl %eax, %esi, %eax13; POSTRA-NEXT: movl (%rdi,%rax,4), %ecx14; POSTRA-NEXT: btrl %esi, %ecx15; POSTRA-NEXT: orl %ecx, %edx16; POSTRA-NEXT: movl %edx, (%rdi,%rax,4)17; POSTRA-NEXT: movq 16(%rdi), %rax18; POSTRA-NEXT: movq (%rdi), %rcx19; POSTRA-NEXT: movq 24(%rdi), %rdx20; POSTRA-NEXT: movq 8(%rdi), %rsi21; POSTRA-NEXT: orq 56(%rdi), %rdx22; POSTRA-NEXT: orq 40(%rdi), %rsi23; POSTRA-NEXT: orq 48(%rdi), %rax24; POSTRA-NEXT: orq 32(%rdi), %rcx25; POSTRA-NEXT: orq %rdx, %rsi26; POSTRA-NEXT: orq %rax, %rcx27; POSTRA-NEXT: orq %rsi, %rcx28; POSTRA-NEXT: setne %al29; POSTRA-NEXT: retq30;31; NOPOSTRA-LABEL: PR166744:32; NOPOSTRA: # %bb.0:33; NOPOSTRA-NEXT: movl %esi, %eax34; NOPOSTRA-NEXT: shrl $3, %esi35; NOPOSTRA-NEXT: andl $60, %esi36; NOPOSTRA-NEXT: movl (%rdi,%rsi), %ecx37; NOPOSTRA-NEXT: btrl %eax, %ecx38; NOPOSTRA-NEXT: shlxl %eax, %edx, %eax39; NOPOSTRA-NEXT: orl %ecx, %eax40; NOPOSTRA-NEXT: movl %eax, (%rdi,%rsi)41; NOPOSTRA-NEXT: movq 16(%rdi), %rax42; NOPOSTRA-NEXT: movq (%rdi), %rcx43; NOPOSTRA-NEXT: movq 8(%rdi), %rdx44; NOPOSTRA-NEXT: movq 24(%rdi), %rsi45; NOPOSTRA-NEXT: orq 56(%rdi), %rsi46; NOPOSTRA-NEXT: orq 40(%rdi), %rdx47; NOPOSTRA-NEXT: orq 48(%rdi), %rax48; NOPOSTRA-NEXT: orq 32(%rdi), %rcx49; NOPOSTRA-NEXT: orq %rsi, %rdx50; NOPOSTRA-NEXT: orq %rax, %rcx51; NOPOSTRA-NEXT: orq %rdx, %rcx52; NOPOSTRA-NEXT: setne %al53; NOPOSTRA-NEXT: retq54 %rem = and i64 %idx, 51155 %sh_prom = zext nneg i64 %rem to i51256 %shl = shl nuw i512 1, %sh_prom57 %not = xor i512 %shl, -158 %load = load i512, ptr %v, align 859 %and = and i512 %load, %not60 %conv2 = zext i1 %b to i51261 %shl4 = shl nuw i512 %conv2, %sh_prom62 %or = or i512 %and, %shl463 store i512 %or, ptr %v, align 864 %cmp = icmp ne i512 %or, 065 ret i1 %cmp66}67