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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX5; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX6 7define <8 x i16> @PR168594() {8; SSE-LABEL: PR168594:9; SSE: # %bb.0:10; SSE-NEXT: pxor %xmm0, %xmm011; SSE-NEXT: psubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm012; SSE-NEXT: retq13;14; AVX-LABEL: PR168594:15; AVX: # %bb.0:16; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm017; AVX-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm018; AVX-NEXT: retq19 %call = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> splat (i16 1), <8 x i16> zeroinitializer)20 %sub = sub <8 x i16> zeroinitializer, %call21 ret <8 x i16> %sub22}23