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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX5; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX6 7define <4 x i16> @PR169205() {8; SSE-LABEL: PR169205:9; SSE: # %bb.0:10; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,1,1,1,u,u,u,u]11; SSE-NEXT: retq12;13; AVX-LABEL: PR169205:14; AVX: # %bb.0:15; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm016; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm017; AVX-NEXT: retq18 %avg = tail call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer)19 %shuffle24 = shufflevector <16 x i8> %avg, <16 x i8> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 9, i32 9>20 %conv25 = zext <4 x i8> %shuffle24 to <4 x i16>21 %not.neg = add <4 x i16> %conv25, splat (i16 1)22 ret <4 x i16> %not.neg23}24