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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mattr=+avx512f | FileCheck %s3; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s4 5target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"6target triple = "x86_64-unknown-linux-gnu"7 8define i64 @foo64(i1 zeroext %i) #0 {9; CHECK-LABEL: foo64:10; CHECK: # %bb.0:11; CHECK-NEXT: movzbl %dil, %eax12; CHECK-NEXT: orq $-2, %rax13; CHECK-NEXT: retq14 br label %bb15 16bb:17 %z = zext i1 %i to i6418 %v = or i64 %z, -219 br label %end20 21end:22 ret i64 %v23}24 25define i16 @foo16(i1 zeroext %i) #0 {26; CHECK-LABEL: foo16:27; CHECK: # %bb.0:28; CHECK-NEXT: movzbl %dil, %eax29; CHECK-NEXT: orl $65534, %eax # imm = 0xFFFE30; CHECK-NEXT: # kill: def $ax killed $ax killed $eax31; CHECK-NEXT: retq32 br label %bb33 34bb:35 %z = zext i1 %i to i1636 %v = or i16 %z, -237 br label %end38 39end:40 ret i16 %v41}42 43define i16 @foo16_1(i1 zeroext %i, i32 %j) #0 {44; CHECK-LABEL: foo16_1:45; CHECK: # %bb.0:46; CHECK-NEXT: movzbl %dil, %eax47; CHECK-NEXT: orl $2, %eax48; CHECK-NEXT: # kill: def $ax killed $ax killed $eax49; CHECK-NEXT: retq50 br label %bb51 52bb:53 %z = zext i1 %i to i1654 %v = or i16 %z, 255 br label %end56 57end:58 ret i16 %v59}60 61define i32 @foo32(i1 zeroext %i) #0 {62; CHECK-LABEL: foo32:63; CHECK: # %bb.0:64; CHECK-NEXT: movzbl %dil, %eax65; CHECK-NEXT: orl $-2, %eax66; CHECK-NEXT: retq67 br label %bb68 69bb:70 %z = zext i1 %i to i3271 %v = or i32 %z, -272 br label %end73 74end:75 ret i32 %v76}77 78define i8 @foo8(i1 zeroext %i) #0 {79; CHECK-LABEL: foo8:80; CHECK: # %bb.0:81; CHECK-NEXT: movl %edi, %eax82; CHECK-NEXT: orb $-2, %al83; CHECK-NEXT: # kill: def $al killed $al killed $eax84; CHECK-NEXT: retq85 br label %bb86 87bb:88 %z = zext i1 %i to i889 %v = or i8 %z, -290 br label %end91 92end:93 ret i8 %v94}95 96