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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 < %s | FileCheck %s3; https://llvm.org/bugs/show_bug.cgi?id=284444 5; extract_vector_elt is allowed to have a different result type than6; the vector scalar type.7; This uses both8; i8 = extract_vector_elt v1i1, Constant:i64<0>9; i1 = extract_vector_elt v1i1, Constant:i64<0>10 11define void @extractelt_mismatch_vector_element_type(i32 %arg, i1 %x) {12; CHECK-LABEL: extractelt_mismatch_vector_element_type:13; CHECK: # %bb.0: # %bb14; CHECK-NEXT: movb $1, %al15; CHECK-NEXT: movb %al, (%rax)16; CHECK-NEXT: movb %al, (%rax)17; CHECK-NEXT: retq18bb:19 %tmp = icmp ult i32 %arg, 020 %tmp2 = insertelement <1 x i1> undef, i1 true, i32 021 %f = insertelement <1 x i1> undef, i1 %x, i32 022 %tmp3 = select i1 %tmp, <1 x i1> %f, <1 x i1> %tmp223 %tmp6 = extractelement <1 x i1> %tmp3, i32 024 br label %bb125 26bb1:27 store volatile <1 x i1> %tmp3, ptr undef28 store volatile i1 %tmp6, ptr undef29 ret void30}31 32