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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX5126 7define <4 x float> @PR32368_128(<4 x float>) {8; SSE-LABEL: PR32368_128:9; SSE: # %bb.0:10; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm011; SSE-NEXT: addps %xmm0, %xmm012; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm013; SSE-NEXT: retq14;15; AVX1-LABEL: PR32368_128:16; AVX1: # %bb.0:17; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm018; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm019; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm020; AVX1-NEXT: retq21;22; AVX2-LABEL: PR32368_128:23; AVX2: # %bb.0:24; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967004,4294967004,4294967004,4294967004]25; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm026; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm027; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [291,291,291,291]28; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm029; AVX2-NEXT: retq30;31; AVX512-LABEL: PR32368_128:32; AVX512: # %bb.0:33; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967004,4294967004,4294967004,4294967004]34; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm035; AVX512-NEXT: vaddps %xmm0, %xmm0, %xmm036; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [291,291,291,291]37; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm038; AVX512-NEXT: retq39 %2 = bitcast <4 x float> %0 to <4 x i32>40 %3 = and <4 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292>41 %4 = bitcast <4 x i32> %3 to <4 x float>42 %5 = fmul <4 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>43 %6 = bitcast <4 x float> %5 to <4 x i32>44 %7 = and <4 x i32> %6, <i32 291, i32 291, i32 291, i32 291>45 %8 = bitcast <4 x i32> %7 to <4 x float>46 ret <4 x float> %847}48 49define <8 x float> @PR32368_256(<8 x float>) {50; SSE-LABEL: PR32368_256:51; SSE: # %bb.0:52; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967004,4294967004,4294967004,4294967004]53; SSE-NEXT: andps %xmm2, %xmm054; SSE-NEXT: andps %xmm2, %xmm155; SSE-NEXT: addps %xmm1, %xmm156; SSE-NEXT: addps %xmm0, %xmm057; SSE-NEXT: movaps {{.*#+}} xmm2 = [291,291,291,291]58; SSE-NEXT: andps %xmm2, %xmm059; SSE-NEXT: andps %xmm2, %xmm160; SSE-NEXT: retq61;62; AVX1-LABEL: PR32368_256:63; AVX1: # %bb.0:64; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm065; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm066; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm067; AVX1-NEXT: retq68;69; AVX2-LABEL: PR32368_256:70; AVX2: # %bb.0:71; AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]72; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm073; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm074; AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [291,291,291,291,291,291,291,291]75; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm076; AVX2-NEXT: retq77;78; AVX512-LABEL: PR32368_256:79; AVX512: # %bb.0:80; AVX512-NEXT: vbroadcastss {{.*#+}} ymm1 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]81; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm082; AVX512-NEXT: vaddps %ymm0, %ymm0, %ymm083; AVX512-NEXT: vbroadcastss {{.*#+}} ymm1 = [291,291,291,291,291,291,291,291]84; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm085; AVX512-NEXT: retq86 %2 = bitcast <8 x float> %0 to <8 x i32>87 %3 = and <8 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292>88 %4 = bitcast <8 x i32> %3 to <8 x float>89 %5 = fmul <8 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>90 %6 = bitcast <8 x float> %5 to <8 x i32>91 %7 = and <8 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291>92 %8 = bitcast <8 x i32> %7 to <8 x float>93 ret <8 x float> %894}95 96define <16 x float> @PR32368_512(<16 x float>) {97; SSE-LABEL: PR32368_512:98; SSE: # %bb.0:99; SSE-NEXT: movaps {{.*#+}} xmm4 = [4294967004,4294967004,4294967004,4294967004]100; SSE-NEXT: andps %xmm4, %xmm0101; SSE-NEXT: andps %xmm4, %xmm1102; SSE-NEXT: andps %xmm4, %xmm2103; SSE-NEXT: andps %xmm4, %xmm3104; SSE-NEXT: addps %xmm3, %xmm3105; SSE-NEXT: addps %xmm2, %xmm2106; SSE-NEXT: addps %xmm1, %xmm1107; SSE-NEXT: addps %xmm0, %xmm0108; SSE-NEXT: movaps {{.*#+}} xmm4 = [291,291,291,291]109; SSE-NEXT: andps %xmm4, %xmm0110; SSE-NEXT: andps %xmm4, %xmm1111; SSE-NEXT: andps %xmm4, %xmm2112; SSE-NEXT: andps %xmm4, %xmm3113; SSE-NEXT: retq114;115; AVX1-LABEL: PR32368_512:116; AVX1: # %bb.0:117; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]118; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0119; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1120; AVX1-NEXT: vaddps %ymm1, %ymm1, %ymm1121; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0122; AVX1-NEXT: vbroadcastss {{.*#+}} ymm2 = [291,291,291,291,291,291,291,291]123; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0124; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1125; AVX1-NEXT: retq126;127; AVX2-LABEL: PR32368_512:128; AVX2: # %bb.0:129; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004]130; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0131; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1132; AVX2-NEXT: vaddps %ymm1, %ymm1, %ymm1133; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0134; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [291,291,291,291,291,291,291,291]135; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0136; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1137; AVX2-NEXT: retq138;139; AVX512-LABEL: PR32368_512:140; AVX512: # %bb.0:141; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0142; AVX512-NEXT: vaddps %zmm0, %zmm0, %zmm0143; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0144; AVX512-NEXT: retq145 %2 = bitcast <16 x float> %0 to <16 x i32>146 %3 = and <16 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292>147 %4 = bitcast <16 x i32> %3 to <16 x float>148 %5 = fmul <16 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>149 %6 = bitcast <16 x float> %5 to <16 x i32>150 %7 = and <16 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291>151 %8 = bitcast <16 x i32> %7 to <16 x float>152 ret <16 x float> %8153}154