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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"5target triple = "x86_64-apple-macosx10.12.0"6 7@a = common local_unnamed_addr global i16 0, align 48@b = common local_unnamed_addr global i16 0, align 49 10define i32 @PR32420() {11; CHECK-LABEL: PR32420:12; CHECK: ## %bb.0:13; CHECK-NEXT: movq _a@GOTPCREL(%rip), %rcx14; CHECK-NEXT: movzwl (%rcx), %eax15; CHECK-NEXT: movl %eax, %edx16; CHECK-NEXT: shll $12, %edx17; CHECK-NEXT: movswl %dx, %edx18; CHECK-NEXT: shrl $12, %edx19; CHECK-NEXT: movq _b@GOTPCREL(%rip), %rsi20; CHECK-NEXT: orw (%rsi), %dx21; CHECK-NEXT: movl (%rcx), %ecx22; CHECK-NEXT: shll $12, %ecx23; CHECK-NEXT: movswl %cx, %ecx24; CHECK-NEXT: shrl $12, %ecx25; CHECK-NEXT: andl %edx, %ecx26; CHECK-NEXT: movw %cx, (%rsi)27; CHECK-NEXT: retq28 %load2 = load i16, ptr @a, align 429 %shl3 = shl i16 %load2, 1230 %ashr4 = ashr i16 %shl3, 1231 %t2 = load volatile i16, ptr @b, align 432 %conv8 = or i16 %t2, %ashr433 %load9 = load i16, ptr @a, align 434 %shl10 = shl i16 %load9, 1235 %ashr11 = ashr i16 %shl10, 1236 %and = and i16 %conv8, %ashr1137 store i16 %and, ptr @b, align 438 %cast1629 = zext i16 %load2 to i3239 ret i32 %cast162940}41