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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=CHECK3 4; This tests for a cyclic dependencies in the generated DAG.5 6@c = external dso_local local_unnamed_addr global i32, align 47@a = external dso_local local_unnamed_addr global i32, align 48@b = external dso_local local_unnamed_addr global i32, align 49 10define void @foo() {11; CHECK-LABEL: foo:12; CHECK: # %bb.0: # %entry13; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax14; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax15; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax16; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax17; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax18; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax19; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax20; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax21; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax22; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax23; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax24; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax25; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax26; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax27; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax28; CHECK-NEXT: movl $0, b(%rip)29; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi30; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi31; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d32; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax33; CHECK-NEXT: cltd34; CHECK-NEXT: idivl a(%rip)35; CHECK-NEXT: movl %eax, %ecx36; CHECK-NEXT: movl c(%rip), %eax37; CHECK-NEXT: cltd38; CHECK-NEXT: idivl %r8d39; CHECK-NEXT: andl %edi, %eax40; CHECK-NEXT: addl %ecx, %eax41; CHECK-NEXT: andl %esi, %eax42; CHECK-NEXT: movl %eax, (%rax)43; CHECK-NEXT: retq44entry:45 %e = alloca i32, align 446 %e.0.e.0.24 = load volatile i32, ptr %e, align 447 %e.0.e.0.25 = load volatile i32, ptr %e, align 448 %e.0.e.0.26 = load volatile i32, ptr %e, align 449 %e.0.e.0.27 = load volatile i32, ptr %e, align 450 %e.0.e.0.28 = load volatile i32, ptr %e, align 451 %e.0.e.0.29 = load volatile i32, ptr %e, align 452 %e.0.e.0.30 = load volatile i32, ptr %e, align 453 %e.0.e.0.31 = load volatile i32, ptr %e, align 454 %e.0.e.0.32 = load volatile i32, ptr %e, align 455 %e.0.e.0.33 = load volatile i32, ptr %e, align 456 %e.0.e.0.34 = load volatile i32, ptr %e, align 457 %e.0.e.0.35 = load volatile i32, ptr %e, align 458 %e.0.e.0.36 = load volatile i32, ptr %e, align 459 %e.0.e.0.37 = load volatile i32, ptr %e, align 460 %e.0.e.0.39 = load volatile i32, ptr %e, align 461 %tmp = load i32, ptr @a, align 462 store i32 0, ptr @b, align 463 %e.0.e.0.41 = load volatile i32, ptr %e, align 464 %add17 = add nsw i32 %e.0.e.0.41, 065 %e.0.e.0.42 = load volatile i32, ptr %e, align 466 %tmp1 = load i32, ptr @c, align 467 %e.0.e.0.43 = load volatile i32, ptr %e, align 468 %div = sdiv i32 %tmp1, %e.0.e.0.4369 %and18 = and i32 %div, %e.0.e.0.4270 %e.0.e.0.44 = load volatile i32, ptr %e, align 471 %div19 = sdiv i32 %e.0.e.0.44, %tmp72 %add20 = add nsw i32 %div19, %and1873 %and21 = and i32 %add20, %add1774 store volatile i32 %and21, ptr undef, align 475 ret void76}77