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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=HSW3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s --check-prefix=ZN4 5define void @_Z15uint64_to_asciimPc(i64 %arg) {6; HSW-LABEL: _Z15uint64_to_asciimPc:7; HSW: # %bb.0: # %bb8; HSW-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD819; HSW-NEXT: movq %rdi, %rdx10; HSW-NEXT: mulxq %rax, %rax, %rax11; HSW-NEXT: shrq $42, %rax12; HSW-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A113; HSW-NEXT: shrq $20, %rax14; HSW-NEXT: leal (%rax,%rax,4), %eax15; HSW-NEXT: addl $5, %eax16; HSW-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF17; HSW-NEXT: leal (%rax,%rax,4), %eax18; HSW-NEXT: shrl $26, %eax19; HSW-NEXT: orb $48, %al20; HSW-NEXT: movb %al, (%rax)21; HSW-NEXT: retq22;23; ZN-LABEL: _Z15uint64_to_asciimPc:24; ZN: # %bb.0: # %bb25; ZN-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD8126; ZN-NEXT: movq %rdi, %rdx27; ZN-NEXT: mulxq %rax, %rax, %rax28; ZN-NEXT: shrq $42, %rax29; ZN-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A130; ZN-NEXT: shrq $20, %rax31; ZN-NEXT: leal 5(%rax,%rax,4), %eax32; ZN-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF33; ZN-NEXT: leal (%rax,%rax,4), %eax34; ZN-NEXT: shrl $26, %eax35; ZN-NEXT: orb $48, %al36; ZN-NEXT: movb %al, (%rax)37; ZN-NEXT: retq38bb:39 %tmp = udiv i64 %arg, 10000000000000040 %tmp1 = mul nuw nsw i64 %tmp, 28147497741 %tmp2 = lshr i64 %tmp1, 2042 %tmp3 = trunc i64 %tmp2 to i3243 %tmp4 = add nuw nsw i32 %tmp3, 144 %tmp5 = and i32 %tmp4, 26843545545 %tmp6 = mul nuw nsw i32 %tmp5, 546 %tmp7 = and i32 %tmp6, 13421772747 %tmp8 = mul nuw nsw i32 %tmp7, 548 %tmp9 = lshr i32 %tmp8, 2649 %tmp10 = trunc i32 %tmp9 to i850 %tmp11 = or i8 %tmp10, 4851 store i8 %tmp11, ptr undef, align 152 ret void53}54