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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=false | FileCheck %s --check-prefix=NO-POSTRA3; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=true | FileCheck %s --check-prefix=POSTRA4 5define float @PR35982_emms(<1 x i64>) nounwind {6; NO-POSTRA-LABEL: PR35982_emms:7; NO-POSTRA: # %bb.0:8; NO-POSTRA-NEXT: subl $8, %esp9; NO-POSTRA-NEXT: movl {{[0-9]+}}(%esp), %eax10; NO-POSTRA-NEXT: movq {{[0-9]+}}(%esp), %mm011; NO-POSTRA-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]12; NO-POSTRA-NEXT: movd %mm0, %ecx13; NO-POSTRA-NEXT: emms14; NO-POSTRA-NEXT: movl %eax, (%esp)15; NO-POSTRA-NEXT: fildl (%esp)16; NO-POSTRA-NEXT: movl %ecx, {{[0-9]+}}(%esp)17; NO-POSTRA-NEXT: fiaddl {{[0-9]+}}(%esp)18; NO-POSTRA-NEXT: addl $8, %esp19; NO-POSTRA-NEXT: retl20;21; POSTRA-LABEL: PR35982_emms:22; POSTRA: # %bb.0:23; POSTRA-NEXT: subl $8, %esp24; POSTRA-NEXT: movq {{[0-9]+}}(%esp), %mm025; POSTRA-NEXT: movl {{[0-9]+}}(%esp), %eax26; POSTRA-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]27; POSTRA-NEXT: movd %mm0, %ecx28; POSTRA-NEXT: emms29; POSTRA-NEXT: movl %eax, (%esp)30; POSTRA-NEXT: fildl (%esp)31; POSTRA-NEXT: movl %ecx, {{[0-9]+}}(%esp)32; POSTRA-NEXT: fiaddl {{[0-9]+}}(%esp)33; POSTRA-NEXT: addl $8, %esp34; POSTRA-NEXT: retl35 %2 = bitcast <1 x i64> %0 to <2 x i32>36 %3 = extractelement <2 x i32> %2, i32 037 %4 = extractelement <1 x i64> %0, i32 038 %5 = bitcast i64 %4 to <1 x i64>39 %6 = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> %5, <1 x i64> %5)40 %7 = bitcast <1 x i64> %6 to <2 x i32>41 %8 = extractelement <2 x i32> %7, i32 042 tail call void @llvm.x86.mmx.emms()43 %9 = sitofp i32 %3 to float44 %10 = sitofp i32 %8 to float45 %11 = fadd float %9, %1046 ret float %1147}48 49declare <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64>, <1 x i64>)50declare void @llvm.x86.mmx.emms()51