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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefix=AVX5124; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512fp16 | FileCheck %s --check-prefix=AVX512FP165 6; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch.7define void @constant_fold_vector_to_half() {8; SSE2-LABEL: constant_fold_vector_to_half:9; SSE2: # %bb.0:10; SSE2-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x400011; SSE2-NEXT: pinsrw $0, -{{[0-9]+}}(%rsp), %xmm012; SSE2-NEXT: pextrw $0, %xmm0, %eax13; SSE2-NEXT: movw %ax, (%rax)14; SSE2-NEXT: retq15;16; AVX512-LABEL: constant_fold_vector_to_half:17; AVX512: # %bb.0:18; AVX512-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x400019; AVX512-NEXT: vpinsrw $0, -{{[0-9]+}}(%rsp), %xmm0, %xmm020; AVX512-NEXT: vpextrw $0, %xmm0, (%rax)21; AVX512-NEXT: retq22;23; AVX512FP16-LABEL: constant_fold_vector_to_half:24; AVX512FP16: # %bb.0:25; AVX512FP16-NEXT: movw $16384, -{{[0-9]+}}(%rsp) # imm = 0x400026; AVX512FP16-NEXT: vmovsh -{{[0-9]+}}(%rsp), %xmm027; AVX512FP16-NEXT: vmovsh %xmm0, (%rax)28; AVX512FP16-NEXT: retq29 store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), ptr undef30 ret void31}32 33; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing.34define void @pr38533_2(half %x) {35; SSE2-LABEL: pr38533_2:36; SSE2: # %bb.0:37; SSE2-NEXT: pextrw $0, %xmm0, %eax38; SSE2-NEXT: movw %ax, (%rax)39; SSE2-NEXT: retq40;41; AVX512-LABEL: pr38533_2:42; AVX512: # %bb.0:43; AVX512-NEXT: vpextrw $0, %xmm0, (%rax)44; AVX512-NEXT: retq45;46; AVX512FP16-LABEL: pr38533_2:47; AVX512FP16: # %bb.0:48; AVX512FP16-NEXT: vmovsh %xmm0, (%rax)49; AVX512FP16-NEXT: retq50 %a = bitcast half %x to <4 x i4>51 store volatile <4 x i4> %a, ptr undef52 ret void53}54 55; This case is a bitcast from fp16 to a 16-bit wide legal vector type. In this case the result type is legal when the bitcast gets type legalized.56define void @pr38533_3(half %x) {57; SSE2-LABEL: pr38533_3:58; SSE2: # %bb.0:59; SSE2-NEXT: pextrw $0, %xmm0, %eax60; SSE2-NEXT: movw %ax, (%rax)61; SSE2-NEXT: retq62;63; AVX512-LABEL: pr38533_3:64; AVX512: # %bb.0:65; AVX512-NEXT: vpextrw $0, %xmm0, (%rax)66; AVX512-NEXT: retq67;68; AVX512FP16-LABEL: pr38533_3:69; AVX512FP16: # %bb.0:70; AVX512FP16-NEXT: vmovsh %xmm0, (%rax)71; AVX512FP16-NEXT: retq72 %a = bitcast half %x to <16 x i1>73 store volatile <16 x i1> %a, ptr undef74 ret void75}76