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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_mem_shuffle2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s3 4define <2 x i64> @test5(ptr %base, <2 x i64> %src0) {5; CHECK-LABEL: test5:6; CHECK: # %bb.0:7; CHECK-NEXT: vpinsrq $1, (%rdi), %xmm0, %xmm08; CHECK-NEXT: retq9 %res = call <2 x i64> @llvm.masked.expandload.v2i64(ptr %base, <2 x i1> <i1 false, i1 true>, <2 x i64> %src0)10 ret <2 x i64>%res11}12declare <2 x i64> @llvm.masked.expandload.v2i64(ptr, <2 x i1>, <2 x i64>)13 14define void @test11(ptr %base, <2 x i64> %V, <2 x i1> %mask) {15; CHECK-LABEL: test11:16; CHECK: # %bb.0:17; CHECK-NEXT: vpsllq $63, %xmm1, %xmm118; CHECK-NEXT: vmovmskpd %xmm1, %eax19; CHECK-NEXT: testb $1, %al20; CHECK-NEXT: jne .LBB1_121; CHECK-NEXT: # %bb.2: # %else22; CHECK-NEXT: testb $2, %al23; CHECK-NEXT: jne .LBB1_324; CHECK-NEXT: .LBB1_4: # %else225; CHECK-NEXT: retq26; CHECK-NEXT: .LBB1_1: # %cond.store27; CHECK-NEXT: vmovq %xmm0, (%rdi)28; CHECK-NEXT: addq $8, %rdi29; CHECK-NEXT: testb $2, %al30; CHECK-NEXT: je .LBB1_431; CHECK-NEXT: .LBB1_3: # %cond.store132; CHECK-NEXT: vpextrq $1, %xmm0, (%rdi)33; CHECK-NEXT: retq34 call void @llvm.masked.compressstore.v2i64(<2 x i64> %V, ptr %base, <2 x i1> %mask)35 ret void36}37declare void @llvm.masked.compressstore.v2i64(<2 x i64>, ptr , <2 x i1>)38