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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=x86_64-- -mattr=+avx2 -run-pass=peephole-opt -o - %s | FileCheck %s3 4# When trying to coalesce the operand of VMOVSDto64rr, a query would5# be made with the same register class but the source has a6# subregister and the result does not.7---8name: uncoalescable_copy_queries_same_regclass_with_only_one_subreg9tracksRegLiveness: true10isSSA: true11body: |12 bb.0:13 liveins: $rax14 15 ; CHECK-LABEL: name: uncoalescable_copy_queries_same_regclass_with_only_one_subreg16 ; CHECK: liveins: $rax17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rax19 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY [[COPY]].sub_32bit20 ; CHECK-NEXT: [[VMOVSDto64rr:%[0-9]+]]:gr64 = VMOVSDto64rr [[COPY1]]21 ; CHECK-NEXT: RET 0, implicit [[VMOVSDto64rr]]22 %0:gr64 = COPY $rax23 %1:vr128 = COPY %0.sub_32bit24 %2:gr64 = VMOVSDto64rr %125 RET 0, implicit %226 27...28