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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=sse | FileCheck %s3 4define i32 @test_load(ptr %a) {5; CHECK-LABEL: test_load:6; CHECK: ## %bb.0: ## %start7; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax8; CHECK-NEXT: movaps (%eax), %xmm09; CHECK-NEXT: movmskps %xmm0, %eax10; CHECK-NEXT: retl11start:12 %0 = load <4 x i32>, ptr %a, align 1613 %1 = icmp slt <4 x i32> %0, zeroinitializer14 %2 = bitcast <4 x i1> %1 to i415 %3 = zext i4 %2 to i3216 ret i32 %317}18 19define i32 @test_bitcast(<4 x float> %a) {20; CHECK-LABEL: test_bitcast:21; CHECK: ## %bb.0: ## %start22; CHECK-NEXT: movmskps %xmm0, %eax23; CHECK-NEXT: retl24start:25 %0 = bitcast <4 x float> %a to <4 x i32>26 %1 = icmp slt <4 x i32> %0, zeroinitializer27 %2 = bitcast <4 x i1> %1 to i428 %3 = zext i4 %2 to i3229 ret i32 %330}31 32define i32 @test_and(<4 x float> %a, <4 x float> %b) {33; CHECK-LABEL: test_and:34; CHECK: ## %bb.0: ## %start35; CHECK-NEXT: andps %xmm1, %xmm036; CHECK-NEXT: movmskps %xmm0, %eax37; CHECK-NEXT: retl38start:39 %0 = bitcast <4 x float> %a to <4 x i32>40 %1 = bitcast <4 x float> %b to <4 x i32>41 %2 = icmp slt <4 x i32> %0, zeroinitializer42 %3 = icmp slt <4 x i32> %1, zeroinitializer43 %4 = and <4 x i1> %2, %344 %5 = bitcast <4 x i1> %4 to i445 %6 = zext i4 %5 to i3246 ret i32 %647}48 49define i32 @test_or(<4 x float> %a, <4 x float> %b) {50; CHECK-LABEL: test_or:51; CHECK: ## %bb.0: ## %start52; CHECK-NEXT: orps %xmm1, %xmm053; CHECK-NEXT: movmskps %xmm0, %eax54; CHECK-NEXT: retl55start:56 %0 = bitcast <4 x float> %a to <4 x i32>57 %1 = bitcast <4 x float> %b to <4 x i32>58 %2 = icmp slt <4 x i32> %0, zeroinitializer59 %3 = icmp slt <4 x i32> %1, zeroinitializer60 %4 = or <4 x i1> %2, %361 %5 = bitcast <4 x i1> %4 to i462 %6 = zext i4 %5 to i3263 ret i32 %664}65 66define i32 @test_xor(<4 x float> %a, <4 x float> %b) {67; CHECK-LABEL: test_xor:68; CHECK: ## %bb.0: ## %start69; CHECK-NEXT: xorps %xmm1, %xmm070; CHECK-NEXT: movmskps %xmm0, %eax71; CHECK-NEXT: retl72start:73 %0 = bitcast <4 x float> %a to <4 x i32>74 %1 = bitcast <4 x float> %b to <4 x i32>75 %2 = icmp slt <4 x i32> %0, zeroinitializer76 %3 = icmp slt <4 x i32> %1, zeroinitializer77 %4 = xor <4 x i1> %2, %378 %5 = bitcast <4 x i1> %4 to i479 %6 = zext i4 %5 to i3280 ret i32 %681}82