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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s3 4%v8_uniform_FVector3 = type { float, float, float }5 6declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>)7 8define void @foo(ptr %Out, ptr %In, <8 x i32> %__mask) {9; CHECK-LABEL: foo:10; CHECK: # %bb.0: # %allocas11; CHECK-NEXT: vmovups (%rsi), %xmm012; CHECK-NEXT: vhaddps 32(%rsi), %xmm0, %xmm013; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,0,1,1]14; CHECK-NEXT: vhaddps %ymm0, %ymm0, %ymm015; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm116; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm017; CHECK-NEXT: vmovss %xmm0, (%rdi)18; CHECK-NEXT: vzeroupper19; CHECK-NEXT: retq20allocas:21 %ptr_masked_load74 = load <8 x float>, ptr %In, align 422 %ptr8096 = getelementptr float, ptr %In, i64 823 %ptr80_masked_load82 = load <8 x float>, ptr %ptr8096, align 424 %ret_7.i.i = shufflevector <8 x float> %ptr_masked_load74, <8 x float> %ptr80_masked_load82, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>25 %v1.i.i100 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %ret_7.i.i, <8 x float> %ret_7.i.i)26 %v2.i.i101 = tail call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %v1.i.i100, <8 x float> %v1.i.i100)27 %scalar1.i.i102 = extractelement <8 x float> %v2.i.i101, i32 028 %scalar2.i.i103 = extractelement <8 x float> %v2.i.i101, i32 429 %sum.i.i104 = fadd float %scalar1.i.i102, %scalar2.i.i10330 store float %sum.i.i104, ptr %Out, align 431 ret void32}33