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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X643; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=X644; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=X645; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X646; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=X647; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X868 9declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)10declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)11declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)12 13; All four versions are semantically equivalent and should produce same asm as scalar version.14 15define i1 @intrinsic_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {16; X64-LABEL: intrinsic_v2i8:17; X64: # %bb.0: # %bb18; X64-NEXT: movzwl (%rsi), %eax19; X64-NEXT: cmpw (%rdi), %ax20; X64-NEXT: sete %al21; X64-NEXT: retq22;23; X86-LABEL: intrinsic_v2i8:24; X86: # %bb.0: # %bb25; X86-NEXT: movl {{[0-9]+}}(%esp), %eax26; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx27; X86-NEXT: movzwl (%ecx), %ecx28; X86-NEXT: cmpw (%eax), %cx29; X86-NEXT: sete %al30; X86-NEXT: retl31bb:32 %lhs = load <2 x i8>, ptr %arg1, align 133 %rhs = load <2 x i8>, ptr %arg, align 134 %cmp = icmp eq <2 x i8> %lhs, %rhs35 %all_eq = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %cmp)36 ret i1 %all_eq37}38 39define i1 @intrinsic_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {40; X64-LABEL: intrinsic_v4i8:41; X64: # %bb.0: # %bb42; X64-NEXT: movl (%rsi), %eax43; X64-NEXT: cmpl (%rdi), %eax44; X64-NEXT: sete %al45; X64-NEXT: retq46;47; X86-LABEL: intrinsic_v4i8:48; X86: # %bb.0: # %bb49; X86-NEXT: movl {{[0-9]+}}(%esp), %eax50; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx51; X86-NEXT: movl (%ecx), %ecx52; X86-NEXT: cmpl (%eax), %ecx53; X86-NEXT: sete %al54; X86-NEXT: retl55bb:56 %lhs = load <4 x i8>, ptr %arg1, align 157 %rhs = load <4 x i8>, ptr %arg, align 158 %cmp = icmp eq <4 x i8> %lhs, %rhs59 %all_eq = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %cmp)60 ret i1 %all_eq61}62 63define i1 @intrinsic_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {64; X64-LABEL: intrinsic_v8i8:65; X64: # %bb.0: # %bb66; X64-NEXT: movq (%rsi), %rax67; X64-NEXT: cmpq (%rdi), %rax68; X64-NEXT: sete %al69; X64-NEXT: retq70;71; X86-LABEL: intrinsic_v8i8:72; X86: # %bb.0: # %bb73; X86-NEXT: movl {{[0-9]+}}(%esp), %eax74; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx75; X86-NEXT: movl (%ecx), %edx76; X86-NEXT: movl 4(%ecx), %ecx77; X86-NEXT: xorl 4(%eax), %ecx78; X86-NEXT: xorl (%eax), %edx79; X86-NEXT: orl %ecx, %edx80; X86-NEXT: sete %al81; X86-NEXT: retl82bb:83 %lhs = load <8 x i8>, ptr %arg1, align 184 %rhs = load <8 x i8>, ptr %arg, align 185 %cmp = icmp eq <8 x i8> %lhs, %rhs86 %all_eq = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %cmp)87 ret i1 %all_eq88}89 90define i1 @vector_version_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {91; X64-LABEL: vector_version_v2i8:92; X64: # %bb.0: # %bb93; X64-NEXT: movzwl (%rsi), %eax94; X64-NEXT: cmpw (%rdi), %ax95; X64-NEXT: sete %al96; X64-NEXT: retq97;98; X86-LABEL: vector_version_v2i8:99; X86: # %bb.0: # %bb100; X86-NEXT: movl {{[0-9]+}}(%esp), %eax101; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx102; X86-NEXT: movzwl (%ecx), %ecx103; X86-NEXT: cmpw (%eax), %cx104; X86-NEXT: sete %al105; X86-NEXT: retl106bb:107 %lhs = load <2 x i8>, ptr %arg1, align 1108 %rhs = load <2 x i8>, ptr %arg, align 1109 %any_ne = icmp ne <2 x i8> %lhs, %rhs110 %any_ne_scalar = bitcast <2 x i1> %any_ne to i2111 %all_eq = icmp eq i2 %any_ne_scalar, 0112 ret i1 %all_eq113}114 115define i1 @vector_version_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {116; X64-LABEL: vector_version_v4i8:117; X64: # %bb.0: # %bb118; X64-NEXT: movl (%rsi), %eax119; X64-NEXT: cmpl (%rdi), %eax120; X64-NEXT: sete %al121; X64-NEXT: retq122;123; X86-LABEL: vector_version_v4i8:124; X86: # %bb.0: # %bb125; X86-NEXT: movl {{[0-9]+}}(%esp), %eax126; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx127; X86-NEXT: movl (%ecx), %ecx128; X86-NEXT: cmpl (%eax), %ecx129; X86-NEXT: sete %al130; X86-NEXT: retl131bb:132 %lhs = load <4 x i8>, ptr %arg1, align 1133 %rhs = load <4 x i8>, ptr %arg, align 1134 %any_ne = icmp ne <4 x i8> %lhs, %rhs135 %any_ne_scalar = bitcast <4 x i1> %any_ne to i4136 %all_eq = icmp eq i4 %any_ne_scalar, 0137 ret i1 %all_eq138}139 140define i1 @vector_version_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {141; X64-LABEL: vector_version_v8i8:142; X64: # %bb.0: # %bb143; X64-NEXT: movq (%rsi), %rax144; X64-NEXT: cmpq (%rdi), %rax145; X64-NEXT: sete %al146; X64-NEXT: retq147;148; X86-LABEL: vector_version_v8i8:149; X86: # %bb.0: # %bb150; X86-NEXT: movl {{[0-9]+}}(%esp), %eax151; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx152; X86-NEXT: movl (%ecx), %edx153; X86-NEXT: movl 4(%ecx), %ecx154; X86-NEXT: xorl 4(%eax), %ecx155; X86-NEXT: xorl (%eax), %edx156; X86-NEXT: orl %ecx, %edx157; X86-NEXT: sete %al158; X86-NEXT: retl159bb:160 %lhs = load <8 x i8>, ptr %arg1, align 1161 %rhs = load <8 x i8>, ptr %arg, align 1162 %any_ne = icmp ne <8 x i8> %lhs, %rhs163 %any_ne_scalar = bitcast <8 x i1> %any_ne to i8164 %all_eq = icmp eq i8 %any_ne_scalar, 0165 ret i1 %all_eq166}167 168define i1 @mixed_version_v2i8(ptr align 1 %arg, ptr align 1 %arg1) {169; X64-LABEL: mixed_version_v2i8:170; X64: # %bb.0: # %bb171; X64-NEXT: movzwl (%rsi), %eax172; X64-NEXT: cmpw (%rdi), %ax173; X64-NEXT: sete %al174; X64-NEXT: retq175;176; X86-LABEL: mixed_version_v2i8:177; X86: # %bb.0: # %bb178; X86-NEXT: movl {{[0-9]+}}(%esp), %eax179; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx180; X86-NEXT: movzwl (%ecx), %ecx181; X86-NEXT: cmpw (%eax), %cx182; X86-NEXT: sete %al183; X86-NEXT: retl184bb:185 %lhs = load <2 x i8>, ptr %arg1, align 1186 %rhs = load <2 x i8>, ptr %arg, align 1187 %lhs_s = bitcast <2 x i8> %lhs to i16188 %rhs_s = bitcast <2 x i8> %rhs to i16189 %all_eq = icmp eq i16 %lhs_s, %rhs_s190 ret i1 %all_eq191}192 193define i1 @mixed_version_v4i8(ptr align 1 %arg, ptr align 1 %arg1) {194; X64-LABEL: mixed_version_v4i8:195; X64: # %bb.0: # %bb196; X64-NEXT: movl (%rsi), %eax197; X64-NEXT: cmpl (%rdi), %eax198; X64-NEXT: sete %al199; X64-NEXT: retq200;201; X86-LABEL: mixed_version_v4i8:202; X86: # %bb.0: # %bb203; X86-NEXT: movl {{[0-9]+}}(%esp), %eax204; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx205; X86-NEXT: movl (%ecx), %ecx206; X86-NEXT: cmpl (%eax), %ecx207; X86-NEXT: sete %al208; X86-NEXT: retl209bb:210 %lhs = load <4 x i8>, ptr %arg1, align 1211 %rhs = load <4 x i8>, ptr %arg, align 1212 %lhs_s = bitcast <4 x i8> %lhs to i32213 %rhs_s = bitcast <4 x i8> %rhs to i32214 %all_eq = icmp eq i32 %lhs_s, %rhs_s215 ret i1 %all_eq216}217 218define i1 @mixed_version_v8i8(ptr align 1 %arg, ptr align 1 %arg1) {219; X64-LABEL: mixed_version_v8i8:220; X64: # %bb.0: # %bb221; X64-NEXT: movq (%rsi), %rax222; X64-NEXT: cmpq (%rdi), %rax223; X64-NEXT: sete %al224; X64-NEXT: retq225;226; X86-LABEL: mixed_version_v8i8:227; X86: # %bb.0: # %bb228; X86-NEXT: movl {{[0-9]+}}(%esp), %eax229; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx230; X86-NEXT: movl (%ecx), %edx231; X86-NEXT: movl 4(%ecx), %ecx232; X86-NEXT: xorl 4(%eax), %ecx233; X86-NEXT: xorl (%eax), %edx234; X86-NEXT: orl %ecx, %edx235; X86-NEXT: sete %al236; X86-NEXT: retl237bb:238 %lhs = load <8 x i8>, ptr %arg1, align 1239 %rhs = load <8 x i8>, ptr %arg, align 1240 %lhs_s = bitcast <8 x i8> %lhs to i64241 %rhs_s = bitcast <8 x i8> %rhs to i64242 %all_eq = icmp eq i64 %lhs_s, %rhs_s243 ret i1 %all_eq244}245 246define i1 @scalar_version_i16(ptr align 1 %arg, ptr align 1 %arg1) {247; X64-LABEL: scalar_version_i16:248; X64: # %bb.0: # %bb249; X64-NEXT: movzwl (%rsi), %eax250; X64-NEXT: cmpw (%rdi), %ax251; X64-NEXT: sete %al252; X64-NEXT: retq253;254; X86-LABEL: scalar_version_i16:255; X86: # %bb.0: # %bb256; X86-NEXT: movl {{[0-9]+}}(%esp), %eax257; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx258; X86-NEXT: movzwl (%ecx), %ecx259; X86-NEXT: cmpw (%eax), %cx260; X86-NEXT: sete %al261; X86-NEXT: retl262bb:263 %lhs = load i16, ptr %arg1, align 1264 %rhs = load i16, ptr %arg, align 1265 %all_eq = icmp eq i16 %lhs, %rhs266 ret i1 %all_eq267}268 269define i1 @scalar_version_i32(ptr align 1 %arg, ptr align 1 %arg1) {270; X64-LABEL: scalar_version_i32:271; X64: # %bb.0: # %bb272; X64-NEXT: movl (%rsi), %eax273; X64-NEXT: cmpl (%rdi), %eax274; X64-NEXT: sete %al275; X64-NEXT: retq276;277; X86-LABEL: scalar_version_i32:278; X86: # %bb.0: # %bb279; X86-NEXT: movl {{[0-9]+}}(%esp), %eax280; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx281; X86-NEXT: movl (%ecx), %ecx282; X86-NEXT: cmpl (%eax), %ecx283; X86-NEXT: sete %al284; X86-NEXT: retl285bb:286 %lhs = load i32, ptr %arg1, align 1287 %rhs = load i32, ptr %arg, align 1288 %all_eq = icmp eq i32 %lhs, %rhs289 ret i1 %all_eq290}291 292define i1 @scalar_version_i64(ptr align 1 %arg, ptr align 1 %arg1) {293; X64-LABEL: scalar_version_i64:294; X64: # %bb.0: # %bb295; X64-NEXT: movq (%rsi), %rax296; X64-NEXT: cmpq (%rdi), %rax297; X64-NEXT: sete %al298; X64-NEXT: retq299;300; X86-LABEL: scalar_version_i64:301; X86: # %bb.0: # %bb302; X86-NEXT: movl {{[0-9]+}}(%esp), %eax303; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx304; X86-NEXT: movl (%ecx), %edx305; X86-NEXT: movl 4(%ecx), %ecx306; X86-NEXT: xorl 4(%eax), %ecx307; X86-NEXT: xorl (%eax), %edx308; X86-NEXT: orl %ecx, %edx309; X86-NEXT: sete %al310; X86-NEXT: retl311bb:312 %lhs = load i64, ptr %arg1, align 1313 %rhs = load i64, ptr %arg, align 1314 %all_eq = icmp eq i64 %lhs, %rhs315 ret i1 %all_eq316}317