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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s3 4define void @main.41() local_unnamed_addr #1 {5; CHECK-LABEL: main.41:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vpbroadcastw (%rax), %ymm08; CHECK-NEXT: vmovdqu (%rax), %ymm19; CHECK-NEXT: vmovdqa {{.*#+}} ymm2 = [31,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14]10; CHECK-NEXT: vpermi2w %ymm0, %ymm1, %ymm211; CHECK-NEXT: vcvtph2ps %ymm2, %zmm012; CHECK-NEXT: vcvtph2ps %ymm1, %zmm113; CHECK-NEXT: vcmpeqps %zmm0, %zmm1, %k114; CHECK-NEXT: vmovdqu8 {{.*#+}} xmm0 {%k1} {z} = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]15; CHECK-NEXT: vmovdqa %xmm0, (%rax)16; CHECK-NEXT: vzeroupper17; CHECK-NEXT: retq18entry:19 %.pre = load half, ptr undef, align 1620 %vector.recur.init = insertelement <16 x half> poison, half %.pre, i64 1521 %wide.load = load <16 x half>, ptr undef, align 222 %0 = shufflevector <16 x half> %vector.recur.init, <16 x half> %wide.load, <16 x i32> <i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>23 %1 = fcmp oeq <16 x half> %wide.load, %024 %2 = zext <16 x i1> %1 to <16 x i8>25 store <16 x i8> %2, ptr undef, align 1626 ret void27}28 29attributes #1 = { nounwind uwtable "target-cpu"="skx" }30