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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3 4declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #05declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #06 7define void @SHA256_Compress_Generic(ptr noundef %ctx) #1 {8; CHECK-LABEL: SHA256_Compress_Generic:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: movl 0, %eax11; CHECK-NEXT: #APP12; CHECK-NEXT: bswapl %eax13; CHECK-NEXT: #NO_APP14; CHECK-NEXT: movl 12(%rdi), %ecx15; CHECK-NEXT: #APP16; CHECK-NEXT: bswapl %ecx17; CHECK-NEXT: #NO_APP18; CHECK-NEXT: vmovd %eax, %xmm019; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,0,1,2,3,128,128,128,128,128,128,128,128]20; CHECK-NEXT: vpshufb %xmm1, %xmm0, %xmm221; CHECK-NEXT: vpsrld $17, %xmm2, %xmm022; CHECK-NEXT: vpslld $15, %xmm2, %xmm323; CHECK-NEXT: vpor %xmm0, %xmm3, %xmm324; CHECK-NEXT: vpsrld $19, %xmm2, %xmm025; CHECK-NEXT: vpslld $13, %xmm2, %xmm426; CHECK-NEXT: vpor %xmm0, %xmm4, %xmm027; CHECK-NEXT: vpxor %xmm0, %xmm3, %xmm028; CHECK-NEXT: vpxor %xmm2, %xmm0, %xmm029; CHECK-NEXT: vmovd %ecx, %xmm430; CHECK-NEXT: vpshufb %xmm1, %xmm4, %xmm131; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm132; CHECK-NEXT: vpsrld $17, %xmm1, %xmm033; CHECK-NEXT: vpslld $15, %xmm1, %xmm434; CHECK-NEXT: vpor %xmm0, %xmm4, %xmm035; CHECK-NEXT: vpsrld $19, %xmm1, %xmm436; CHECK-NEXT: vpslld $13, %xmm1, %xmm537; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm438; CHECK-NEXT: vpxor %xmm4, %xmm0, %xmm039; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm040; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm041; CHECK-NEXT: vpsrld $17, %xmm0, %xmm442; CHECK-NEXT: vpslld $15, %xmm0, %xmm543; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm444; CHECK-NEXT: vpsrld $19, %xmm0, %xmm545; CHECK-NEXT: vpslld $13, %xmm0, %xmm646; CHECK-NEXT: vpor %xmm5, %xmm6, %xmm547; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm448; CHECK-NEXT: vpsrld $10, %xmm0, %xmm049; CHECK-NEXT: vpxor %xmm0, %xmm4, %xmm050; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm051; CHECK-NEXT: vpsrld $17, %xmm0, %xmm452; CHECK-NEXT: vpslld $15, %xmm0, %xmm553; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm454; CHECK-NEXT: vpsrld $19, %xmm0, %xmm555; CHECK-NEXT: vpslld $13, %xmm0, %xmm656; CHECK-NEXT: vpor %xmm5, %xmm6, %xmm557; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm458; CHECK-NEXT: vpsrld $10, %xmm0, %xmm559; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm460; CHECK-NEXT: vpblendd {{.*#+}} xmm2 = xmm3[0],xmm2[1],xmm3[2,3]61; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,0,2,3]62; CHECK-NEXT: vpaddd %xmm4, %xmm2, %xmm263; CHECK-NEXT: vpsrld $17, %xmm2, %xmm364; CHECK-NEXT: vpslld $15, %xmm2, %xmm465; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm366; CHECK-NEXT: vpsrld $19, %xmm2, %xmm467; CHECK-NEXT: vpslld $13, %xmm2, %xmm568; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm469; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm370; CHECK-NEXT: vpsrld $10, %xmm2, %xmm271; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm272; CHECK-NEXT: vpsrlq $32, %xmm1, %xmm373; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm174; CHECK-NEXT: vpsrld $17, %xmm1, %xmm275; CHECK-NEXT: vpslld $15, %xmm1, %xmm476; CHECK-NEXT: vpor %xmm2, %xmm4, %xmm277; CHECK-NEXT: vpsrld $19, %xmm1, %xmm478; CHECK-NEXT: vpslld $13, %xmm1, %xmm579; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm480; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm281; CHECK-NEXT: vpsrld $10, %xmm1, %xmm482; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm283; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm284; CHECK-NEXT: vpsrld $17, %xmm2, %xmm385; CHECK-NEXT: vpslld $15, %xmm2, %xmm486; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm387; CHECK-NEXT: vpsrld $19, %xmm2, %xmm488; CHECK-NEXT: vpslld $13, %xmm2, %xmm589; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm490; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm391; CHECK-NEXT: vpsrld $10, %xmm2, %xmm292; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm293; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm094; CHECK-NEXT: vpsrld $17, %xmm0, %xmm295; CHECK-NEXT: vpslld $15, %xmm0, %xmm396; CHECK-NEXT: vpor %xmm2, %xmm3, %xmm297; CHECK-NEXT: vpsrld $19, %xmm0, %xmm398; CHECK-NEXT: vpslld $13, %xmm0, %xmm499; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3100; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2101; CHECK-NEXT: vpsrld $10, %xmm0, %xmm3102; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2103; CHECK-NEXT: vpsllq $32, %xmm1, %xmm3104; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2105; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0106; CHECK-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]107; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]108; CHECK-NEXT: vmovdqu %ymm0, 132(%rdi)109; CHECK-NEXT: vzeroupper110; CHECK-NEXT: retq111entry:112 %0 = load i32, ptr null, align 4113 %1 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %0) #3114 %arrayidx14 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 3115 %2 = load i32, ptr %arrayidx14, align 4116 %3 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %2) #3117 %4 = insertelement <2 x i32> zeroinitializer, i32 %1, i64 1118 %5 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 15, i32 15>)119 %6 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 13, i32 13>)120 %7 = xor <2 x i32> %5, %6121 %8 = lshr <2 x i32> %4, zeroinitializer122 %9 = xor <2 x i32> %7, %8123 %10 = insertelement <2 x i32> zeroinitializer, i32 %3, i64 0124 %11 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %10, <2 x i32> <i32 1, i32 2>125 %12 = add <2 x i32> %11, %9126 %13 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 15, i32 15>)127 %14 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 13, i32 13>)128 %15 = xor <2 x i32> %13, %14129 %16 = lshr <2 x i32> %12, zeroinitializer130 %17 = xor <2 x i32> %15, %16131 %18 = add <2 x i32> %4, %17132 %19 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 15, i32 15>)133 %20 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 13, i32 13>)134 %21 = xor <2 x i32> %19, %20135 %22 = lshr <2 x i32> %18, <i32 10, i32 10>136 %23 = xor <2 x i32> %21, %22137 %24 = add <2 x i32> %4, %23138 %25 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 15, i32 15>)139 %26 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 13, i32 13>)140 %27 = xor <2 x i32> %25, %26141 %28 = lshr <2 x i32> %24, <i32 10, i32 10>142 %29 = xor <2 x i32> %27, %28143 %30 = shufflevector <2 x i32> %4, <2 x i32> %12, <2 x i32> <i32 1, i32 2>144 %31 = add <2 x i32> %30, %29145 %32 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 15, i32 15>)146 %33 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 13, i32 13>)147 %34 = xor <2 x i32> %32, %33148 %35 = lshr <2 x i32> %31, <i32 10, i32 10>149 %36 = xor <2 x i32> %34, %35150 %37 = shufflevector <2 x i32> %12, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 2>151 %38 = add <2 x i32> %37, %36152 %arrayidx918 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 33153 store <2 x i32> %38, ptr %arrayidx918, align 4154 %arrayidx1012 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 35155 %39 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 15, i32 15>)156 %40 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 13, i32 13>)157 %41 = xor <2 x i32> %39, %40158 %42 = lshr <2 x i32> %38, <i32 10, i32 10>159 %43 = xor <2 x i32> %41, %42160 %44 = add <2 x i32> %37, %43161 store <2 x i32> zeroinitializer, ptr %arrayidx1012, align 4162 %arrayidx1106 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 37163 %45 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 15, i32 15>)164 %46 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 13, i32 13>)165 %47 = xor <2 x i32> %45, %46166 %48 = lshr <2 x i32> %44, <i32 10, i32 10>167 %49 = xor <2 x i32> %47, %48168 %50 = lshr <2 x i32> %24, zeroinitializer169 %51 = add <2 x i32> %50, %49170 store <2 x i32> %51, ptr %arrayidx1106, align 4171 %arrayidx1200 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 39172 %52 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 15, i32 15>)173 %53 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 13, i32 13>)174 %54 = xor <2 x i32> %52, %53175 %55 = lshr <2 x i32> %51, <i32 10, i32 10>176 %56 = xor <2 x i32> %54, %55177 %57 = shufflevector <2 x i32> %38, <2 x i32> zeroinitializer, <2 x i32> <i32 poison, i32 0>178 %58 = insertelement <2 x i32> %57, i32 0, i64 0179 %59 = add <2 x i32> %58, %56180 store <2 x i32> %59, ptr %arrayidx1200, align 4181 ret void182 183; uselistorder directives184 uselistorder <2 x i32> %4, { 7, 0, 1, 6, 5, 4, 3, 2 }185 uselistorder <2 x i32> %38, { 6, 5, 4, 3, 2, 1, 0 }186}187 188declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #2189 190; uselistorder directives191uselistorder ptr @llvm.fshl.v2i32, { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 }192 193attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }194attributes #1 = { nounwind sspstrong memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "probe-stack"="inline-asm" "stack-protector-buffer-size"="8" "target-cpu"="skylake" "target-features"="+adx,+aes,+avx,+avx2,+bmi,+bmi2,+clflushopt,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" }195attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }196attributes #3 = { nounwind memory(none) }197