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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE4; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX5; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX6 7define void @PR72539(<8 x i32> %insertelement){8; SSE-LABEL: PR72539:9; SSE: # %bb.0:10; SSE-NEXT: xorb $7, 011; SSE-NEXT: retq12;13; AVX-LABEL: PR72539:14; AVX: # %bb.0:15; AVX-NEXT: movzbl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax16; AVX-NEXT: xorb %al, 017; AVX-NEXT: retq18 %load671 = load i8, ptr addrspace(1) null, align 119 %shufflevector = shufflevector <8 x i32> %insertelement, <8 x i32> zeroinitializer, <8 x i32> zeroinitializer20 %xor68 = xor <8 x i32> %shufflevector, <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>21 %call69 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %xor68)22 %trunc70 = trunc i32 %call69 to i823 %xor71 = xor i8 %load671, %trunc7024 store i8 %xor71, ptr addrspace(1) null, align 125 ret void26}27declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)28