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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX4 5define void @main(<16 x i32> %0, i32 %1) {6; SSE-LABEL: main:7; SSE: # %bb.0: # %entry8; SSE-NEXT: movd %edi, %xmm49; SSE-NEXT: movsd {{.*#+}} xmm0 = [0,1,0,0]10; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,0]11; SSE-NEXT: paddd %xmm0, %xmm012; SSE-NEXT: paddd %xmm1, %xmm113; SSE-NEXT: paddd %xmm3, %xmm314; SSE-NEXT: paddd %xmm2, %xmm215; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,1,3]16; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[1,0]17; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]18; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[1,0]19; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[1,3]20; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm3[1,0]21; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[1,3]22; SSE-NEXT: xorps %xmm2, %xmm023; SSE-NEXT: xorps %xmm4, %xmm124; SSE-NEXT: xorps %xmm0, %xmm125; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]26; SSE-NEXT: pxor %xmm1, %xmm027; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]28; SSE-NEXT: pxor %xmm0, %xmm129; SSE-NEXT: movd %xmm1, 030; SSE-NEXT: retq31;32; AVX-LABEL: main:33; AVX: # %bb.0: # %entry34; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm235; AVX-NEXT: movl $1, %eax36; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm237; AVX-NEXT: vpinsrd $3, %edi, %xmm2, %xmm238; AVX-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5,6,7]39; AVX-NEXT: vpaddd %ymm2, %ymm2, %ymm240; AVX-NEXT: vpaddd %ymm1, %ymm1, %ymm341; AVX-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]42; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[3,3,3,3,7,7,7,7]43; AVX-NEXT: vpaddd %ymm0, %ymm0, %ymm044; AVX-NEXT: vpshufd {{.*#+}} ymm1 = ymm3[0,1,1,3,4,5,5,7]45; AVX-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]46; AVX-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,1,3,3,5,5,7]47; AVX-NEXT: vpermd %ymm2, %ymm1, %ymm148; AVX-NEXT: vpxor %ymm0, %ymm1, %ymm049; AVX-NEXT: vextracti128 $1, %ymm0, %xmm150; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm051; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]52; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm053; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]54; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm055; AVX-NEXT: vmovd %xmm0, 056; AVX-NEXT: vzeroupper57; AVX-NEXT: retq58entry:59 %2 = insertelement <16 x i32> %0, i32 1, i64 160 %3 = insertelement <16 x i32> %2, i32 %1, i64 361 %4 = insertelement <16 x i32> %3, i32 0, i64 062 %5 = shl <16 x i32> %4, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>63 %6 = shufflevector <16 x i32> %5, <16 x i32> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15>64 %7 = tail call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %6)65 store i32 %7, ptr null, align 466 ret void67}68declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)69