57 lines · plain
1; RUN-disabled: llc < %s -verify-machineinstrs -mtriple=x86_64-apple-macosx -pre-RA-sched=ilp -debug-only=pre-RA-sched \2; RUN-disabled: 2>&1 | FileCheck %s3; RUN: true4; REQUIRES: asserts5;6; rdar:13279013: pre-RA-sched should not check all interferences and7; repush them on the ready queue after scheduling each instruction.8;9; CHECK: *** List Scheduling10; CHECK: Interfering reg EFLAGS11; CHECK: Repushing12; CHECK: Repushing13; CHECK: Repushing14; CHECK-NOT: Repushing15; CHECK: *** Final schedule16define i32 @test(ptr %pin) #0 {17 %l0 = load i8, ptr %pin, align 118 19 %g1a = getelementptr inbounds i8, ptr %pin, i64 120 %l1a = load i8, ptr %g1a, align 121 %z1a = zext i8 %l1a to i3222 %g1b = getelementptr inbounds i8, ptr %pin, i64 223 %l1b = load i8, ptr %g1b, align 124 %z1b = zext i8 %l1b to i3225 %c1 = icmp ne i8 %l0, 026 %x1 = xor i32 %z1a, %z1b27 %s1 = select i1 %c1, i32 %z1a, i32 %x128 29 %g2a = getelementptr inbounds i8, ptr %pin, i64 330 %l2a = load i8, ptr %g2a, align 131 %z2a = zext i8 %l2a to i3232 %g2b = getelementptr inbounds i8, ptr %pin, i64 433 %l2b = load i8, ptr %g2b, align 134 %z2b = zext i8 %l2b to i3235 %x2 = xor i32 %z2a, %z2b36 %s2 = select i1 %c1, i32 %z2a, i32 %x237 38 %g3a = getelementptr inbounds i8, ptr %pin, i64 539 %l3a = load i8, ptr %g3a, align 140 %z3a = zext i8 %l3a to i3241 %g3b = getelementptr inbounds i8, ptr %pin, i64 642 %l3b = load i8, ptr %g3b, align 143 %z3b = zext i8 %l3b to i3244 %x3 = xor i32 %z3a, %z3b45 %s3 = select i1 %c1, i32 %z3a, i32 %x346 47 %c3 = icmp ne i8 %l1a, 048 %c4 = icmp ne i8 %l2a, 049 50 %s4 = select i1 %c3, i32 %s1, i32 %s251 %s5 = select i1 %c4, i32 %s4, i32 %s352 53 ret i32 %s554}55 56attributes #0 = { nounwind ssp uwtable }57