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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512F6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512FP167 8define <2 x double> @prefer_f32_v2f64(ptr %p) nounwind {9; SSE-LABEL: prefer_f32_v2f64:10; SSE: # %bb.0: # %entry11; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero12; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]13; SSE-NEXT: cvtps2pd %xmm0, %xmm014; SSE-NEXT: retq15;16; AVX-LABEL: prefer_f32_v2f64:17; AVX: # %bb.0: # %entry18; AVX-NEXT: vbroadcastss (%rdi), %xmm019; AVX-NEXT: vcvtps2pd %xmm0, %xmm020; AVX-NEXT: retq21;22; AVX512-LABEL: prefer_f32_v2f64:23; AVX512: # %bb.0: # %entry24; AVX512-NEXT: vcvtps2pd (%rdi){1to2}, %xmm025; AVX512-NEXT: retq26entry:27 %0 = load float, ptr %p, align 428 %vecinit.i = insertelement <2 x float> undef, float %0, i64 029 %vecinit3.i = shufflevector <2 x float> %vecinit.i, <2 x float> poison, <2 x i32> zeroinitializer30 %conv.i = fpext <2 x float> %vecinit3.i to <2 x double>31 ret <2 x double> %conv.i32}33 34define <4 x double> @prefer_f32_v4f64(ptr %p) nounwind {35; SSE-LABEL: prefer_f32_v4f64:36; SSE: # %bb.0: # %entry37; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero38; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]39; SSE-NEXT: cvtps2pd %xmm0, %xmm040; SSE-NEXT: movaps %xmm0, %xmm141; SSE-NEXT: retq42;43; AVX-LABEL: prefer_f32_v4f64:44; AVX: # %bb.0: # %entry45; AVX-NEXT: vbroadcastss (%rdi), %xmm046; AVX-NEXT: vcvtps2pd %xmm0, %ymm047; AVX-NEXT: retq48;49; AVX512-LABEL: prefer_f32_v4f64:50; AVX512: # %bb.0: # %entry51; AVX512-NEXT: vcvtps2pd (%rdi){1to4}, %ymm052; AVX512-NEXT: retq53entry:54 %0 = load float, ptr %p, align 455 %vecinit.i = insertelement <4 x float> undef, float %0, i64 056 %vecinit3.i = shufflevector <4 x float> %vecinit.i, <4 x float> poison, <4 x i32> zeroinitializer57 %conv.i = fpext <4 x float> %vecinit3.i to <4 x double>58 ret <4 x double> %conv.i59}60 61define <4 x float> @prefer_f16_v4f32(ptr %p) nounwind {62; SSE-LABEL: prefer_f16_v4f32:63; SSE: # %bb.0: # %entry64; SSE-NEXT: pushq %rax65; SSE-NEXT: pinsrw $0, (%rdi), %xmm066; SSE-NEXT: callq __extendhfsf2@PLT67; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]68; SSE-NEXT: popq %rax69; SSE-NEXT: retq70;71; AVX1-LABEL: prefer_f16_v4f32:72; AVX1: # %bb.0: # %entry73; AVX1-NEXT: pushq %rax74; AVX1-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm075; AVX1-NEXT: callq __extendhfsf2@PLT76; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]77; AVX1-NEXT: popq %rax78; AVX1-NEXT: retq79;80; AVX2-LABEL: prefer_f16_v4f32:81; AVX2: # %bb.0: # %entry82; AVX2-NEXT: pushq %rax83; AVX2-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm084; AVX2-NEXT: callq __extendhfsf2@PLT85; AVX2-NEXT: vpbroadcastd %xmm0, %xmm086; AVX2-NEXT: popq %rax87; AVX2-NEXT: retq88;89; AVX512F-LABEL: prefer_f16_v4f32:90; AVX512F: # %bb.0: # %entry91; AVX512F-NEXT: vpbroadcastw (%rdi), %xmm092; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm093; AVX512F-NEXT: retq94;95; AVX512FP16-LABEL: prefer_f16_v4f32:96; AVX512FP16: # %bb.0: # %entry97; AVX512FP16-NEXT: vcvtph2psx (%rdi){1to4}, %xmm098; AVX512FP16-NEXT: retq99entry:100 %0 = load half, ptr %p, align 4101 %vecinit.i = insertelement <4 x half> undef, half %0, i64 0102 %vecinit3.i = shufflevector <4 x half> %vecinit.i, <4 x half> poison, <4 x i32> zeroinitializer103 %conv.i = fpext <4 x half> %vecinit3.i to <4 x float>104 ret <4 x float> %conv.i105}106 107define <8 x float> @prefer_f16_v8f32(ptr %p) nounwind {108; SSE-LABEL: prefer_f16_v8f32:109; SSE: # %bb.0: # %entry110; SSE-NEXT: pushq %rax111; SSE-NEXT: pinsrw $0, (%rdi), %xmm0112; SSE-NEXT: callq __extendhfsf2@PLT113; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]114; SSE-NEXT: movaps %xmm0, %xmm1115; SSE-NEXT: popq %rax116; SSE-NEXT: retq117;118; AVX1-LABEL: prefer_f16_v8f32:119; AVX1: # %bb.0: # %entry120; AVX1-NEXT: pushq %rax121; AVX1-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0122; AVX1-NEXT: callq __extendhfsf2@PLT123; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]124; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0125; AVX1-NEXT: popq %rax126; AVX1-NEXT: retq127;128; AVX2-LABEL: prefer_f16_v8f32:129; AVX2: # %bb.0: # %entry130; AVX2-NEXT: pushq %rax131; AVX2-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0132; AVX2-NEXT: callq __extendhfsf2@PLT133; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0134; AVX2-NEXT: popq %rax135; AVX2-NEXT: retq136;137; AVX512F-LABEL: prefer_f16_v8f32:138; AVX512F: # %bb.0: # %entry139; AVX512F-NEXT: vpbroadcastw (%rdi), %xmm0140; AVX512F-NEXT: vcvtph2ps %xmm0, %ymm0141; AVX512F-NEXT: retq142;143; AVX512FP16-LABEL: prefer_f16_v8f32:144; AVX512FP16: # %bb.0: # %entry145; AVX512FP16-NEXT: vcvtph2psx (%rdi){1to8}, %ymm0146; AVX512FP16-NEXT: retq147entry:148 %0 = load half, ptr %p, align 4149 %vecinit.i = insertelement <8 x half> undef, half %0, i64 0150 %vecinit3.i = shufflevector <8 x half> %vecinit.i, <8 x half> poison, <8 x i32> zeroinitializer151 %conv.i = fpext <8 x half> %vecinit3.i to <8 x float>152 ret <8 x float> %conv.i153}154 155define <2 x double> @prefer_f16_v2f64(ptr %p) nounwind {156; SSE-LABEL: prefer_f16_v2f64:157; SSE: # %bb.0: # %entry158; SSE-NEXT: pushq %rax159; SSE-NEXT: pinsrw $0, (%rdi), %xmm0160; SSE-NEXT: callq __extendhfsf2@PLT161; SSE-NEXT: cvtss2sd %xmm0, %xmm0162; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]163; SSE-NEXT: popq %rax164; SSE-NEXT: retq165;166; AVX-LABEL: prefer_f16_v2f64:167; AVX: # %bb.0: # %entry168; AVX-NEXT: pushq %rax169; AVX-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0170; AVX-NEXT: callq __extendhfsf2@PLT171; AVX-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0172; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]173; AVX-NEXT: popq %rax174; AVX-NEXT: retq175;176; AVX512F-LABEL: prefer_f16_v2f64:177; AVX512F: # %bb.0: # %entry178; AVX512F-NEXT: vpbroadcastw (%rdi), %xmm0179; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0180; AVX512F-NEXT: vcvtps2pd %xmm0, %xmm0181; AVX512F-NEXT: retq182;183; AVX512FP16-LABEL: prefer_f16_v2f64:184; AVX512FP16: # %bb.0: # %entry185; AVX512FP16-NEXT: vcvtph2pd (%rdi){1to2}, %xmm0186; AVX512FP16-NEXT: retq187entry:188 %0 = load half, ptr %p, align 4189 %vecinit.i = insertelement <2 x half> undef, half %0, i64 0190 %vecinit3.i = shufflevector <2 x half> %vecinit.i, <2 x half> poison, <2 x i32> zeroinitializer191 %conv.i = fpext <2 x half> %vecinit3.i to <2 x double>192 ret <2 x double> %conv.i193}194 195define <4 x double> @prefer_f16_v4f64(ptr %p) nounwind {196; SSE-LABEL: prefer_f16_v4f64:197; SSE: # %bb.0: # %entry198; SSE-NEXT: pushq %rax199; SSE-NEXT: pinsrw $0, (%rdi), %xmm0200; SSE-NEXT: callq __extendhfsf2@PLT201; SSE-NEXT: cvtss2sd %xmm0, %xmm0202; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]203; SSE-NEXT: movaps %xmm0, %xmm1204; SSE-NEXT: popq %rax205; SSE-NEXT: retq206;207; AVX1-LABEL: prefer_f16_v4f64:208; AVX1: # %bb.0: # %entry209; AVX1-NEXT: pushq %rax210; AVX1-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0211; AVX1-NEXT: callq __extendhfsf2@PLT212; AVX1-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0213; AVX1-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]214; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0215; AVX1-NEXT: popq %rax216; AVX1-NEXT: retq217;218; AVX2-LABEL: prefer_f16_v4f64:219; AVX2: # %bb.0: # %entry220; AVX2-NEXT: pushq %rax221; AVX2-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0222; AVX2-NEXT: callq __extendhfsf2@PLT223; AVX2-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0224; AVX2-NEXT: vbroadcastsd %xmm0, %ymm0225; AVX2-NEXT: popq %rax226; AVX2-NEXT: retq227;228; AVX512F-LABEL: prefer_f16_v4f64:229; AVX512F: # %bb.0: # %entry230; AVX512F-NEXT: vpbroadcastw (%rdi), %xmm0231; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0232; AVX512F-NEXT: vcvtps2pd %xmm0, %ymm0233; AVX512F-NEXT: retq234;235; AVX512FP16-LABEL: prefer_f16_v4f64:236; AVX512FP16: # %bb.0: # %entry237; AVX512FP16-NEXT: vcvtph2pd (%rdi){1to4}, %ymm0238; AVX512FP16-NEXT: retq239entry:240 %0 = load half, ptr %p, align 4241 %vecinit.i = insertelement <4 x half> undef, half %0, i64 0242 %vecinit3.i = shufflevector <4 x half> %vecinit.i, <4 x half> poison, <4 x i32> zeroinitializer243 %conv.i = fpext <4 x half> %vecinit3.i to <4 x double>244 ret <4 x double> %conv.i245}246